Texas Instruments DS90CR286AMTD

Overview

DS90CR286AMTD from Texas Instruments is a 28-bit LVDS-to-LVCMOS deserializer IC used as the receiver in Channel Link I serial interface systems, converting four LVDS data lanes plus one LVDS clock into parallel 28-bit 3.3-V LVCMOS outputs (24-bit RGB + 4 control bits), supporting 20–66 MHz input clock rates and delivering up to 1.848 Gbps throughput for high-resolution display interconnects in automotive infotainment and industrial imaging.

For engineers reviewing the DS90CR286AMTD datasheet, DS90CR286AMTD pinout, DS90CR286AMTD application, or DS90CR286AMTD equivalent, key selection criteria include its 56-pin TSSOP package, LVDS input termination requirements, RxCLKOUT rising-edge strobe timing, RSKM skew margin at 400 ps (66 MHz), and compatibility with DS90CF560/DS90CF562 transmitters in EMI-sensitive video transport designs.

Technical Context

The DS90CR286AMTD implements a fully integrated PLL that locks to incoming LVDS clock (20–66 MHz) without external components, enabling precise sampling of four serialized LVDS data streams-each carrying 7 bits per clock cycle-to reconstruct 28-bit parallel LVCMOS output. Its internal architecture includes five LVDS receivers (four data + one clock), a phase-aligned clock recovery circuit, and 28-channel LVCMOS drivers with programmable power-down via PWR DWN.

It operates across −40°C to +85°C, requires 100-Ω differential termination on all LVDS inputs, and delivers best-in-class setup/hold times (RSRC/RHRC = 4.5/4 ns min at 66 MHz) with <270 mW typical power consumption at 66 MHz. The device supports 3.3-V LVCMOS logic levels and integrates dedicated PLL and LVDS supply domains (PLL VCC/GND, LVDS VCC/GND, VCC, GND).

Key Specifications

Pinout & Package

DS90CR286AMTD is housed in a 56-pin TSSOP (DGG) package measuring 14.00 mm × 6.10 mm, with exposed thermal pad not connected internally. Pin functions are validated per TI SNLS043H datasheet Rev H (Jan 2016), including dedicated supply domains (VCC, LVDS VCC, PLL VCC) and separated ground planes (GND, LVDS GND, PLL GND) for noise isolation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with DS90CR216AMTD, DS90CR286AMTD delivers 24-bit color support and 33% higher throughput but occupies larger PCB area; versus DS90UR905QSQ, it offers proven reliability and lower cost at the expense of bandwidth ceiling and modern packaging.

Availability

DS90CR286AMTD is available at Aetrix Electronics and suitable for automotive infotainment systems, industrial imaging subsystems, and medical display interfaces requiring stable component supply, long-term lifecycle assurance, and traceable sourcing from authorized channels.

Supply support for DS90CR286AMTD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of leadership in high-speed interface solutions.

The DS90CR286AMTD belongs to TI's Channel Link I serializer/deserializer product line, designed specifically to replace wide parallel buses in high-resolution video transport applications where EMI reduction, cable weight savings, and signal integrity are critical.

FAQ

What is the maximum supported pixel clock frequency for DS90CR286AMTD?

The DS90CR286AMTD supports LVDS input clock frequencies from 20 MHz to 66 MHz. At 66 MHz, it achieves 1.848 Gbps aggregate throughput, enabling UXGA (1600×1200) resolution at 60 Hz with 24-bit RGB. Exceeding 66 MHz violates the device's specified operating range and may cause loss of PLL lock or data corruption. DS90CR286AMTD does not support overclocking beyond datasheet limits.

Does DS90CR286AMTD require external termination resistors on LVDS inputs?

Yes, DS90CR286AMTD requires a 100-Ω ±10% differential termination resistor across each LVDS input pair (RxIN0± through RxIN3± and RxCLKIN±). These resistors must be placed as close as possible to the IC pins to minimize stub length and prevent signal reflections. The device itself does not integrate termination; omission causes degraded eye diagrams and potential bit errors.

How does the PWR DWN pin function on DS90CR286AMTD?

The PWR DWN pin on DS90CR286AMTD is an active-low LVCMOS input that places the device into ultra-low-power mode when driven low. In this state, all RxOUT outputs are forced low, RxCLK OUT stops toggling, and supply current drops to ≤55 μA. The pin has no hysteresis and must be held statically; floating or noisy signals may cause unintended mode transitions. DS90CR286AMTD resumes normal operation within 1 μs after PWR DWN is released high.

What is the meaning of RSKM in DS90CR286AMTD specifications?

RSKM (Receiver Skew Margin) for DS90CR286AMTD is the valid time window - 400 ps at 66 MHz - during which LVDS data can be sampled correctly despite interconnect skew, cable length variation, and clock jitter. It quantifies timing robustness for system-level layout: designers must ensure total skew (trace mismatch + jitter + ISI) stays below this margin. DS90CR286AMTD's RSKM directly impacts maximum allowable cable length and routing asymmetry in real-world deployments.

Can DS90CR286AMTD be used with non-TI transmitters?

DS90CR286AMTD is compatible with any TIA/EIA-644-compliant LVDS transmitter that outputs four serialized data lanes plus one clock at 20–66 MHz, provided the transmitter adheres to Channel Link I timing conventions (e.g., 7-bit serialization per clock cycle). While optimized for TI transmitters like DS90CF560/DS90CF562, interoperability depends on meeting setup/hold, jitter, and pulse-position specs - not vendor lock-in. Validation with third-party transmitters is recommended per application requirements.