Texas Instruments DS90CR286AMTDX/NOPB

Overview

DS90CR286AMTDX/NOPB from Texas Instruments is a 28-bit LVDS-to-LVCMOS deserializer IC used as a high-speed video interface receiver in display subsystems. It converts four LVDS data lanes plus one LVDS clock (20–66 MHz) into 28 parallel 3.3-V LVCMOS outputs - including 24-bit RGB and 4 control bits (HSYNC, VSYNC, DE, CNTL) - for driving TFT LCD panels. It features an internal PLL with no external components, <270 mW typical power at 66 MHz, and supports automotive-grade operation via pin-compatible Q1 variant.

For engineers reviewing the DS90CR286AMTDX/NOPB datasheet, DS90CR286AMTDX/NOPB pinout, DS90CR286AMTDX/NOPB application, or DS90CR286AMTDX/NOPB equivalent, key selection criteria include LVDS input skew margin (400 ps at 66 MHz), RxOUT setup/hold timing (4.5–7.3 ns / 4–6.3 ns), 56-pin TSSOP package compatibility, and functional alignment with DS90CR285 transmitter-based Channel Link I systems.

Technical Context

The DS90CR286AMTDX/NOPB implements a fixed-ratio deserialization architecture: each 66 MHz LVDS clock cycle yields seven serial bits per LVDS lane, reconstructing 28 parallel LVCMOS outputs synchronized to the rising edge of RxCLK OUT. Its PLL locks to incoming LVDS clock without external components and maintains <250 ps cycle-to-cycle jitter when paired with compliant transmitters.

It integrates five LVDS receivers (four data + one clock), a serial-to-parallel converter, and 28-channel LVCMOS drivers with programmable power-down (PWR DWN). All LVCMOS outputs are 3.3-V compatible, with VIH ≥ 2 V, VOL ≤ 0.3 V at 2 mA, and RSKM validated for interconnect skew up to 40 ps/ft on PCB traces or shielded cables.

Key Specifications

Pinout & Package

DS90CR286AMTDX/NOPB uses a 56-pin TSSOP (DGG) package measuring 14.00 mm × 6.10 mm, with exposed thermal pad not connected internally. Power domains are segregated: LVDS inputs (LVDS VCC/GND), PLL (PLL VCC/GND), and LVCMOS outputs (VCC/GND) each have dedicated supply pins to minimize noise coupling.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with DS90CR286AQMT, the DS90CR286AMTDX/NOPB offers identical electrical performance and pin compatibility but excludes automotive qualification; versus DS90UR241QRTVT, it provides native 28-bit + control signal support and simpler PLL implementation at lower bandwidth.

Availability

DS90CR286AMTDX/NOPB is available at Aetrix Electronics and suitable for automotive infotainment displays, industrial TFT LCD modules, and digital signage backplanes requiring stable component supply across multi-year production cycles.

Supply support for DS90CR286AMTDX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in interface, power management, and signal chain solutions.

The DS90CR286AMTDX/NOPB belongs to TI's Channel Link I serializer/deserializer product line, designed specifically for high-reliability, low-EMI video transport in automotive, industrial, and medical display systems.

FAQ

What is the maximum data rate supported by DS90CR286AMTDX/NOPB?

DS90CR286AMTDX/NOPB supports an LVDS clock input up to 66 MHz, resulting in a maximum aggregate data rate of 1.848 Gbps (4 × 462 Mbps per LVDS lane). Each lane carries 7 bits per clock cycle, reconstructed into 28 parallel LVCMOS outputs. This enables full HD (1920×1080) video at 60 Hz with embedded sync signals. The DS90CR286AMTDX/NOPB datasheet specifies RSKM and timing margins validated at this maximum rate.

Does DS90CR286AMTDX/NOPB require external components for PLL operation?

No, DS90CR286AMTDX/NOPB integrates a fully self-contained PLL that locks to the incoming LVDS clock without any external capacitors, resistors, or crystal. The PLL is optimized for 20–66 MHz input and generates a low-jitter RxCLK OUT with 50% duty cycle. External 100-Ω termination resistors are required only on LVDS input pairs, not for PLL functionality. This simplifies layout and reduces BOM count for the DS90CR286AMTDX/NOPB.

How does the power-down mode function on DS90CR286AMTDX/NOPB?

Asserting the PWR DWN pin low places DS90CR286AMTDX/NOPB into power-down mode, reducing supply current to <55 μA while forcing all 28 RxOUT signals low. The device retains its configuration and resumes normal operation within 1 μs after PWR DWN is deasserted. This feature enables dynamic power gating in battery-powered or thermally constrained displays. During power-down, the DS90CR286AMTDX/NOPB does not drive RxCLK OUT and ignores LVDS input activity.

What are the key timing parameters for interfacing DS90CR286AMTDX/NOPB with an FPGA or timing controller?

Key timing parameters for DS90CR286AMTDX/NOPB include RxOUT setup time (RSRC = 4.5–7.3 ns) and hold time (RHRC = 4–6.3 ns) relative to RxCLK OUT rising edge, plus RxCLK OUT period (15–50 ns) and high/low times (5–7.6 ns / 5–6.3 ns at 66 MHz). These values ensure reliable capture by downstream logic. The DS90CR286AMTDX/NOPB also guarantees RSPos0 = 0.7–1.4 ns at 66 MHz, defining the earliest valid sampling point for bit 0.

Is DS90CR286AMTDX/NOPB pin-compatible with any automotive-qualified variants?

Yes, DS90CR286AMTDX/NOPB is pin-compatible with DS90CR286AQMT, which is AEC-Q100 Grade 3 qualified (−40°C to 105°C) and shares identical pinout, electrical specifications, and functional behavior. Both use the same 56-pin TSSOP (DGG) package and support identical 28-bit deserialization. The DS90CR286AQMT differs only in temperature rating and qualification testing - no PCB redesign is needed when upgrading to automotive grade.