Texas Instruments DS90CR286AQMT/NOPB

Overview

DS90CR286AQMT/NOPB from Texas Instruments is a 28-bit LVDS-to-LVCMOS deserializer IC used as a high-speed serial link receiver in display interface systems. It converts four LVDS data lanes plus one LVDS clock into 28 parallel 3.3-V LVCMOS outputs (24-bit RGB + 4 control bits), supports 20–66 MHz input clock rates, delivers ≤1.848 Gbps throughput at 66 MHz, and operates across −40°C to +85°C for automotive-grade display interconnects.

For engineers reviewing the DS90CR286AQMT/NOPB datasheet, DS90CR286AQMT/NOPB pinout, DS90CR286AQMT/NOPB application, or DS90CR286AQMT/NOPB equivalent, this page provides verified technical context, real-world timing margins, power-down behavior, LVDS termination requirements, and validated alternative receivers for display interface design.

Technical Context

The DS90CR286AQMT/NOPB implements a fully integrated PLL that locks to incoming LVDS clock (20–66 MHz) without external components and generates a clean, low-jitter RxCLKOUT with 50% duty cycle. It samples four serialized LVDS data streams-each carrying seven bits per clock cycle-and reconstructs them into 28-bit parallel LVCMOS outputs strobed on the rising edge of RxCLKOUT.

Its internal architecture includes five LVDS differential receivers (four data + one clock), a serial-to-parallel converter, and 28 LVCMOS output drivers. The device achieves best-in-class setup/hold times (RSRC/RHRC = 4.5–7.3 ns at 66 MHz) and provides ≥400 ps receiver skew margin (RSKM) to accommodate cable/PCB interconnect skew and transmitter jitter.

Key Specifications

Pinout & Package

DS90CR286AQMT/NOPB uses a 56-pin TSSOP (DGG) package measuring 14.00 mm × 6.10 mm, with dedicated power/ground domains for LVCMOS outputs, LVDS inputs, and PLL circuitry to minimize noise coupling.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with DS90CR286A-Q1, DS90CR286AQMT/NOPB offers identical electrical performance and layout compatibility but lacks extended temperature certification; compared with DS90UR241QSQ/NOPB, it provides full 28-bit mapping including control signals but operates at lower maximum frequency and lacks equalization.

Availability

DS90CR286AQMT/NOPB is available at Aetrix Electronics and suitable for automotive infotainment, industrial LCD panel interconnect, and medical imaging display applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for DS90CR286AQMT/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies, with leadership in high-reliability interface ICs for automotive and industrial markets.

The DS90CR286AQMT/NOPB belongs to TI's Channel Link I deserializer product line, designed specifically to replace wide parallel RGB buses with noise-immune, space-efficient LVDS serial links in display subsystems.

FAQ

What is the maximum supported clock frequency for DS90CR286AQMT/NOPB?

The DS90CR286AQMT/NOPB supports an LVDS input clock frequency range of 20 MHz to 66 MHz. At 66 MHz, each of its four LVDS data lanes operates at 462 Mbps, delivering a total throughput of 1.848 Gbps. Operation above 66 MHz is not specified or guaranteed per the official datasheet SNLS043H.

Does DS90CR286AQMT/NOPB require external termination resistors?

Yes, DS90CR286AQMT/NOPB requires a 100-Ω ±10% resistor across each LVDS differential pair (RxIN0+/− through RxIN3+/− and RxCLKIN+/−). These resistors must be placed as close as possible to the IC pins to maintain signal integrity and minimize reflections on the LVDS lines.

How does the power-down mode function on DS90CR286AQMT/NOPB?

Asserting the PWR DWN pin low places DS90CR286AQMT/NOPB into power-down mode, reducing supply current to <55 μA max. In this state, all RxOUT[27:0] outputs are driven low, and the internal PLL stops. The device resumes normal operation within 10 ms after PWR DWN is deasserted.

What is the meaning of RSKM in DS90CR286AQMT/NOPB specifications?

RSKM (Receiver Skew Margin) is the valid data sampling window at DS90CR286AQMT/NOPB inputs, defined as ≥400 ps at 66 MHz. It accounts for LVDS interconnect skew, transmitter pulse position variation, and clock jitter, ensuring robust deserialization even with imperfect cabling or board layout.

Can DS90CR286AQMT/NOPB be used with a 21-bit source transmitter?

No - DS90CR286AQMT/NOPB is a 28-bit receiver designed for use with 28-bit transmitters like DS90CR285A. For 21-bit systems, TI specifies DS90CR216A. Using DS90CR286AQMT/NOPB with a 21-bit source would leave 7 output bits unconnected or misaligned, risking incorrect display timing or color mapping.