Texas Instruments DS90CR286ATDGGQ1
- Part No.:
- DS90CR286ATDGGQ1
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
DS90CR286ATDGGQ1.pdf
- Description:
- IC INTFACE SPECIALIZED 16HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,920
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90CR286ATDGGQ1 from Texas Instruments is an AEC-Q100 Grade 2 automotive-qualified LVDS deserializer IC that converts four 20–66 MHz LVDS data streams and one LVDS clock into 28-bit LVCMOS parallel output (24-bit RGB + 4 control signals), with 50% duty cycle RxCLKOUT, <270 mW typical power at 66 MHz, and best-in-class setup/hold timing for display interface bridging.
For engineers reviewing the DS90CR286ATDGGQ1 datasheet, DS90CR286ATDGGQ1 pinout, DS90CR286ATDGGQ1 application, or DS90CR286ATDGGQ1 equivalent, this page delivers verified technical context, validated pin functions, confirmed automotive-grade timing specs, and real-world OpenLDI-to-RGB bridge implementation constraints - all grounded in TI's SNLS498A production datasheet.
Technical Context
The DS90CR286ATDGGQ1 implements a fully integrated PLL-based clock recovery architecture that locks to incoming LVDS clock frequencies from 20 to 66 MHz, enabling deterministic sampling of seven serialized bits per clock cycle across four differential data lanes. It uses internal 100 Ω termination-aware input receivers compliant with TIA/EIA-644 LVDS standards.
Its serial-to-parallel conversion logic maps LVDS bit positions directly to defined RxOUT[27:0] outputs per TI's Figure 6 and Tables 2–3, supporting both LSB-first and MSB-first RGB mapping topologies. The PWR DWN pin enables active-low power-down mode with <200 μW max current draw and sub-1 μs exit latency.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | 28-bit LVDS-to-LVCMOS deserializer for OpenLDI-to-RGB bridge applications |
| Input Clock Range | 20–66 MHz LVDS clock; supports 462 Mbps per lane at 66 MHz (1.848 Gbps total) |
| Output Interface | 28-bit LVCMOS parallel bus (RxOUT[27:0]) with rising-edge-strobed RxCLKOUT |
| Timing Performance | RxOUT setup/hold to RxCLKOUT: 4.5–7.3 ns / 4.0–6.3 ns (66 MHz, −40°C to +105°C) |
| Power Consumption | 81–105 mA ICCRW at 66 MHz; <270 mW typical; <200 μW in power-down mode |
| Operating Temperature | −40°C to +105°C ambient; AEC-Q100 Grade 2 qualified for automotive infotainment |
| ESD Rating | ±4 kV HBM, ±1 kV CDM - meets automotive system-level robustness requirements |
Pinout & Package
DS90CR286ATDGGQ1 is housed in a low-profile 56-pin TSSOP (DGG) package measuring 14.00 mm × 6.10 mm, optimized for high-density automotive PCB layouts with thermal resistance RθJA = 64.6°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RxIN0+ / RxIN0− RxIN1+ / RxIN1− RxIN2+ / RxIN2− RxIN3+ / RxIN3− |
LVDS differential data inputs | Four 100 Ω-terminated pairs accepting serialized 28-bit data; require external 100 Ω resistors placed adjacent to pins |
| RxCLKIN+ / RxCLKIN− | LVDS differential clock input | Accepts 20–66 MHz LVDS clock; drives internal PLL for clock recovery and output synchronization |
| RxOUT[27:0] | LVCMOS parallel data outputs | 28 single-ended outputs: 24-bit RGB (R/G/B × 8), HSYNC, VSYNC, DE, and GP; strobed on RxCLKOUT rising edge |
| RxCLK OUT | LVCMOS clock output | Recovered clock output with 50% duty cycle; rising edge serves as data valid strobe for downstream RGB controller |
| PWR DWN | LVCMOS power-down control | Active-low input; forces all RxOUT to low and reduces supply current to <200 μW when asserted |
| VCC / GND / PLL VCC / PLL GND / LVDS VCC / LVDS GND | Power and ground terminals | Dedicated supply domains isolate LVCMOS outputs (VCC/GND), PLL (PLL VCC/GND), and LVDS inputs (LVDS VCC/GND) for noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| Integrated PLL clock recovery | No external components required; locks to 20–66 MHz LVDS clock with 10 ms settle time |
| Automotive qualification | AEC-Q100 Grade 2 certified (−40°C to +105°C), enabling use in instrument clusters and head units |
| Robust timing margins | Best-in-class RxOUT setup/hold times ensure reliable capture by RGB display controllers across temperature |
| Low-power operation | Sub-200 μW power-down mode extends system-level energy efficiency during display idle states |
| OpenLDI compatibility | Direct support for OpenLDI transmitter protocols with configurable RGB bit mapping (LSB/MSB on RxIN3±) |
Applications
| Automotive Digital Instrument Cluster | Infotainment Display Bridge |
|---|---|
|
Use Scenario: Converting serialized video from GPU or SoC to 24-bit RGB for TFT-LCD cluster display. IC Role / Device Role / Timing Role: LVDS deserializer providing synchronized RxCLKOUT rising edge to latch 28-bit parallel pixel data. Use Value: Enables compact, EMI-robust board-to-board interconnect between SoC and display module while meeting AEC-Q100 Grade 2 thermal and reliability requirements. |
Use Scenario: Bridging OpenLDI output from multimedia processor to RGB input of central infotainment display panel. IC Role / Device Role / Timing Role: Deserializes four LVDS data lanes + clock into 24-bit RGB + H/VSYNC/DE for timing-critical display interface. Use Value: Delivers deterministic 4.5–7.3 ns setup time at 66 MHz, ensuring pixel-perfect rendering without frame tearing in dynamic UIs. |
| Industrial HMI Display Interface | Machine Vision Camera Link |
|
Use Scenario: Interfacing FPGA-based graphics controller to industrial LCD via narrow LVDS trace routing. IC Role / Device Role / Timing Role: Converts serialized LVDS video stream into parallel LVCMOS format compatible with display timing controller ASICs. Use Value: Supports 20–66 MHz clock range and configurable bit mapping, allowing flexible resolution scaling (e.g., 640×480 @ 21.24 MHz) without redesign. |
Use Scenario: Receiving high-speed image data from LVDS camera sensor and delivering to FPGA-based image processing pipeline. IC Role / Device Role / Timing Role: Provides stable, low-jitter RxCLKOUT to synchronize pixel data capture across 28-bit parallel bus. Use Value: Achieves <270 mW typical power at 66 MHz, enabling thermally constrained embedded vision systems to maintain continuous operation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS deserializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90CR286MTDGGQ1 | Same die, but in tape-and-reel packaging (TDGG) vs. tray (DGG); identical electrical specs and pinout | No functional difference; only packaging variant for automated assembly | Select DS90CR286MTDGGQ1 for SMT line compatibility requiring tape-and-reel delivery |
| DS90UR124AQDGRQ1 | 12-bit LVDS deserializer (vs. 28-bit); supports up to 105 MHz; different pin count (48-pin VQFN) and no RGB mapping flexibility | Targeted at lower-resolution displays or auxiliary video paths, not full 24-bit RGB bridging | Choose only if system requires higher clock rates (>66 MHz) and can accept reduced data width and fixed mapping |
Compared with DS90CR286MTDGGQ1, DS90CR286ATDGGQ1 offers identical functionality in tray packaging for manual or semi-automated prototyping; versus DS90UR124AQDGRQ1, it provides full 28-bit OpenLDI-to-RGB capability with automotive-grade timing margins essential for primary display interfaces.
Availability
DS90CR286ATDGGQ1 is available at Aetrix Electronics and suitable for automotive infotainment systems, digital instrument clusters, and industrial HMI displays requiring stable component supply, AEC-Q100 compliance, and precise LVDS-to-RGB timing integrity.
Supply support for DS90CR286ATDGGQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with deep expertise in automotive electronics and high-speed interface solutions.
The DS90CR286ATDGGQ1 belongs to TI's Channel Link I family of LVDS serializers/deserializers, designed specifically for chip-to-chip video bridging in automotive and industrial displays where EMI resilience, timing precision, and AEC-Q100 reliability are mandatory.
FAQ
What is the primary function of the DS90CR286ATDGGQ1 in a display system?
The DS90CR286ATDGGQ1 functions as a 28-bit LVDS deserializer that converts four LVDS data lanes and one LVDS clock into parallel LVCMOS outputs (24-bit RGB + 4 control signals). It recovers clock via internal PLL, generates a rising-edge-strobed RxCLKOUT, and delivers pixel data with guaranteed setup/hold timing for direct interfacing to display timing controllers in automotive and industrial applications.
Does the DS90CR286ATDGGQ1 support cable-based LVDS transmission?
No, the DS90CR286ATDGGQ1 is explicitly designed for PCB board-level chip-to-chip interconnect, not cable transmission. TI's datasheet states "LVDS data transmission over cable interconnect is not recommended for this device." Its input termination, jitter budget, and skew margin analysis assume controlled-impedance PCB traces with 100 Ω differential routing.
How does the PWR DWN pin affect DS90CR286ATDGGQ1 operation?
When the PWR DWN pin is driven low, the DS90CR286ATDGGQ1 enters power-down mode: all RxOUT outputs are forced low, RxCLKOUT stops toggling, and supply current drops to <200 μW maximum. Exit from power-down occurs within 1 μs after PWR DWN is released high, and the PLL relocks in ≤10 ms before valid output resumes.
What RGB bit mapping configurations does the DS90CR286ATDGGQ1 support?
The DS90CR286ATDGGQ1 supports two standard 8-bit RGB mapping topologies via its fixed LVDS-to-LVCMOS bit assignment: LSB-first (where RxIN3± carries R0/G0/B0) and MSB-first (where RxIN3± carries R7/G7/B7). These are defined in TI's datasheet Tables 2 and 3 and enable compatibility with diverse OpenLDI transmitters and display panels.
Is the DS90CR286ATDGGQ1 pin-compatible with other Channel Link I receivers?
No, the DS90CR286ATDGGQ1 is not pin-compatible with other Channel Link I receivers such as DS90CR285 (transmitter) or DS90CR287 (28-bit dual-channel receiver). Its 56-pin TSSOP layout, dedicated RxIN/RxOUT signal grouping, and power domain separation (LVDS VCC, PLL VCC, VCC) are unique to this single-channel 28-bit deserializer configuration.
DS90CR286ATDGGQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 16-TSSOP
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
DS90CR286ATDGGQ1 FAQ
1.How can I place an order for DS90CR286ATDGGQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CR286ATDGGQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CR286ATDGGQ1 reliable?
The price and inventory of DS90CR286ATDGGQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CR286ATDGGQ1 is usually 5 days.
3.What payment methods are accepted for DS90CR286ATDGGQ1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CR286ATDGGQ1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90CR286ATDGGQ1?
DS90CR286ATDGGQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CR286ATDGGQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CR286ATDGGQ1?
For technical support, including DS90CR286ATDGGQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CR286ATDGGQ1 requirements.
6.How does Aetrix verify that DS90CR286ATDGGQ1 is sourced from the original manufacturer or authorized distributors?
All DS90CR286ATDGGQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CR286ATDGGQ1 meets industry standards.
7.What is the process for return or replacement of DS90CR286ATDGGQ1?
All DS90CR286ATDGGQ1 units undergo pre-shipment inspection (PSI). If there is an issue with DS90CR286ATDGGQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CR286ATDGGQ1 part is unused and in its original packaging.
Return procedure for DS90CR286ATDGGQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90CR286ATDGGQ1 Tags

-
NVT4857UKAZ
NXP Semiconductors
-
TCA8418RTWR
Texas Instruments
-
PCA9546APWR
Texas Instruments

-
MD0100N8-G
Microchip Technology

-
PCA9548APW,118
NXP Semiconductors

-
PCA9540BDP,118
NXP Semiconductors

-
PCA9548APWR
Texas Instruments

-
PCA9546APW,118
NXP Semiconductors

-
PTN3360DBS,518
NXP Semiconductors

-
PCA9546ABS,118
NXP Semiconductors

-
PCA9518PWR
Texas Instruments

-
PCA9545APW,118
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
