Texas Instruments DS90CR286ATDGGRQ1

Overview

DS90CR286ATDGGRQ1 from Texas Instruments is an AEC-Q100 Grade 2 automotive-qualified LVDS deserializer IC that converts four 20–66 MHz LVDS data streams and one LVDS clock into 28-bit parallel LVCMOS output (24-bit RGB + 4 control signals), operating at up to 66 MHz with 1.848 Gbps aggregate throughput and <270 mW typical power consumption. It serves as the receiver in OpenLDI-to-RGB bridge applications on PCBs between GPU and display units.

For engineers reviewing the DS90CR286ATDGGRQ1 datasheet, DS90CR286ATDGGRQ1 pinout, DS90CR286ATDGGRQ1 application, or DS90CR286ATDGGRQ1 equivalent, key selection criteria include its 56-pin TSSOP package, −40°C to +105°C operating range, integrated PLL with no external components, 4.5 ns minimum RxOUT setup time at 66 MHz, and compatibility with TIA/EIA-644 LVDS standard.

Technical Context

The DS90CR286ATDGGRQ1 implements a fully integrated PLL-based clock recovery architecture that locks to incoming LVDS clock frequencies from 20 to 66 MHz, enabling precise sampling of seven serialized bits per clock cycle across four differential data lanes. Its internal serial-to-parallel converter maps LVDS bit positions directly to defined RxOUT[27:0] outputs per TI's documented mapping tables for RGB and control signal alignment.

It supports two distinct 8-bit RGB mapping topologies (LSBs or MSBs on RxIN3±), provides a dedicated PWR DWN pin for active-low power-down mode (<200 μW max), and requires 100 Ω differential termination on all five LVDS inputs (four data + one clock) placed adjacent to input pins to maintain signal integrity and minimize skew-induced timing violations.

Key Specifications

Pinout & Package

DS90CR286ATDGGRQ1 is housed in a low-profile 56-pin TSSOP (DGG) package measuring 14.00 mm × 6.10 mm, with exposed thermal pad not connected internally and requiring PCB thermal relief per TI layout guidelines.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with DS90CR286ATDGGRQ1, DS90CR286AQMA/NOPB offers identical performance at lower cost but lacks automotive qualification, while SN65LVDS32PW provides only physical-layer reception-requiring significant additional circuitry to achieve equivalent deserialization functionality.

Availability

DS90CR286ATDGGRQ1 is available at Aetrix Electronics and suitable for automotive infotainment systems, industrial display backplanes, and machine vision camera interfaces requiring stable component supply with guaranteed long-term availability and automotive-grade traceability.

Supply support for DS90CR286ATDGGRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in high-reliability interface solutions for automotive and industrial markets.

The DS90CR286ATDGGRQ1 belongs to TI's Channel Link I family of LVDS serializers/deserializers, designed specifically for chip-to-chip video bridging in automotive displays where robustness, timing precision, and AEC-Q100 compliance are mandatory.

FAQ

What is the primary function of the DS90CR286ATDGGRQ1?

The DS90CR286ATDGGRQ1 is a 28-bit LVDS deserializer IC that receives four LVDS data lanes and one LVDS clock, then reconstructs them into parallel 28-bit LVCMOS output (24-bit RGB + 4 control signals). It features an integrated PLL for clock recovery and is optimized for OpenLDI-to-RGB bridge applications on PCBs. The DS90CR286ATDGGRQ1 operates from 20 to 66 MHz and supports automotive-grade reliability per AEC-Q100 Grade 2.

Does the DS90CR286ATDGGRQ1 require external components for PLL operation?

No, the DS90CR286ATDGGRQ1 integrates a fully self-contained PLL that requires no external capacitors, resistors, or crystals. Its PLL locks automatically to the incoming LVDS clock (20–66 MHz) and generates the stable RxCLK OUT used to strobe the 28-bit LVCMOS outputs. This eliminates BOM cost and layout complexity associated with external loop filters or reference oscillators in the DS90CR286ATDGGRQ1 design.

What are the supported RGB data mappings for the DS90CR286ATDGGRQ1?

The DS90CR286ATDGGRQ1 supports two standardized 8-bit RGB mapping configurations: one with LSBs on RxIN3± and another with MSBs on RxIN3±. These mappings are hardwired and documented in TI's datasheet Tables 2 and 3. The DS90CR286ATDGGRQ1 does not support programmable remapping - correct routing must be implemented at the PCB level based on the chosen topology and display controller requirements.

How does the PWR DWN pin function on the DS90CR286ATDGGRQ1?

The PWR DWN pin on the DS90CR286ATDGGRQ1 is an active-low control input that places the device into ultra-low-power mode when asserted. In this state, all RxOUT outputs are driven low, and supply current drops to <55 μA maximum. The DS90CR286ATDGGRQ1 exits power-down synchronously upon deassertion, with PLL lock reacquired within 10 ms. This feature enables dynamic power management in display subsystems without requiring full reset sequencing.

Is LVDS cable transmission supported with the DS90CR286ATDGGRQ1?

No, the DS90CR286ATDGGRQ1 is explicitly designed for chip-to-chip PCB interconnect-not cable transmission. TI's datasheet states "LVDS data transmission over cable interconnect is not recommended for this device." Signal integrity, skew budget, and jitter performance are optimized for short (<15 cm), controlled-impedance PCB traces with 100 Ω differential routing. Using the DS90CR286ATDGGRQ1 with cables risks timing violations and link failure due to uncontrolled interconnect effects.