Texas Instruments DS90CR286MTD

Overview

DS90CR286MTD from Texas Instruments is a 28-bit LVDS receiver IC that converts four LVDS data streams and one LVDS clock into 28-bit LVCMOS/LVTTL parallel outputs, operating at up to 66 MHz clock frequency with 1.848 Gbps total throughput, 290 mV differential output swing, and −40°C to +85°C industrial temperature range - used in high-speed flat-panel display interconnects and embedded video links.

For engineers reviewing the DS90CR286MTD datasheet, DS90CR286MTD pinout, DS90CR286MTD application, or DS90CR286MTD equivalent, this page delivers verified electrical specs, TSSOP-56 pin mapping, real-world skew margin (400 ps @ 66 MHz), power-down behavior (<0.5 mW), and direct alternatives for Channel Link receiver replacement in compact PCB layouts.

Technical Context

The DS90CR286MTD implements a PLL-based clock recovery architecture to reconstruct the transmit clock from the incoming LVDS clock pair, enabling synchronous sampling of serialized 28-bit data across five differential lanes (four data + one clock). It supports rising-edge data strobe timing with precise input strobe positioning (e.g., RSPos0 = 0.7–1.4 ns @ 66 MHz) and maintains a 400 ps skew margin under worst-case PVT conditions.

Its receiver inputs comply with TIA/EIA-644 LVDS standards, featuring 100 mV differential threshold, ±1.0 V common-mode range centered at +1.2 V, and integrated termination support for 100 Ω differential loads. The device uses dedicated LVDS VCC/GND and PLL VCC/GND rails to isolate noise-sensitive analog circuitry from digital I/O domains.

Key Specifications

Pinout & Package

DS90CR286MTD is housed in a 56-lead Low-Profile TSSOP package (Package Code DGG, R-PDSO-G56), with thermal pad exposed on underside and 0.5 mm lead pitch. Pin layout separates LVDS analog inputs (RxIN+/−, RxCLK IN+/−), TTL outputs (RxOUT[0:27]), power domains (VCC, LVDS VCC, PLL VCC), and ground nets (GND, LVDS GND, PLL GND) to minimize coupling.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with DS90CR286MTD, DS90CR286MTDX/NOPB offers identical functionality in volume packaging, while SN65LVDS32 lacks serialization/deserialization capability and clock recovery - making it unsuitable as a drop-in replacement but viable for simpler point-to-point LVDS interfaces.

Availability

DS90CR286MTD is available at Aetrix Electronics and suitable for industrial LCD display interface, medical imaging data link, and automotive infotainment head unit applications requiring stable component supply and long-term lifecycle support.

Supply support for DS90CR286MTD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog, embedded processing, and connectivity technologies for industrial, automotive, and communications markets.

The DS90CR286MTD belongs to TI's Channel Link serializer-deserializer product line, designed specifically to replace wide parallel buses with compact, low-EMI LVDS links for high-speed video and graphics transmission in space-constrained systems.

FAQ

What is the maximum supported clock frequency for DS90CR286MTD?

The DS90CR286MTD supports a maximum transmit clock frequency of 66 MHz, enabling a total data throughput of 1.848 Gbps. At this rate, the receiver achieves a 400 ps skew margin and maintains valid sampling windows across PVT variations, as confirmed in the SNLS130C datasheet timing tables for RSPos and RSKM parameters.

Does DS90CR286MTD require external components for PLL operation?

No, DS90CR286MTD integrates a fully self-contained PLL for clock recovery and requires no external capacitors, resistors, or crystals. Its PLL locks to the incoming LVDS clock pair (RxCLK IN+/−) and generates internal timing for deserialization - a key feature documented in the "Features" section and Figure 15 of the SNLS130C datasheet.

What is the recommended termination for DS90CR286MTD LVDS inputs?

DS90CR286MTD LVDS inputs (RxIN+/− and RxCLK IN+/−) require a 100 Ω differential termination resistor placed as close as possible to the input pins. This value matches the typical characteristic impedance of Twin-Coax or twisted-pair cables and is explicitly specified in the "Termination" section of SNLS130C, Figure 23.

How does DS90CR286MTD handle power-down mode?

When PWR DWN is asserted low, DS90CR286MTD drives all 28 RxOUT pins low and reduces total supply current to <0.5 mW. Outputs remain in this defined state until PWR DWN is de-asserted, and internal circuitry resumes operation within 1 μs - timing verified in Figure 19 and Table "RPDD" of SNLS130C.

Is DS90CR286MTD compatible with 5 V logic systems?

No, DS90CR286MTD is not 5 V tolerant. Its RxOUT outputs are LVCMOS/LVTTL compliant with 3.3 V supply (VCC = 3.0–3.6 V), and input pins such as PWR DWN accept only 0–VCC logic levels. Connecting to 5 V systems without level translation risks permanent damage, as stated in the Absolute Maximum Ratings table of SNLS130C.