Texas Instruments DS90CR286MTD/NOPB

Overview

DS90CR286MTD/NOPB from Texas Instruments is a 28-bit LVDS receiver IC that converts four LVDS data streams and one LVDS clock pair back into 28-bit LVCMOS/LVTTL parallel data. It operates at up to 66 MHz transmit clock frequency, delivers 1.848 Gbps aggregate throughput, supports −40°C to +85°C industrial temperature range, and uses a single +3.3V supply. It is used in high-speed video interconnects such as flat-panel display interfaces.

For engineers reviewing the DS90CR286MTD/NOPB datasheet, DS90CR286MTD/NOPB pinout, DS90CR286MTD/NOPB application, or DS90CR286MTD/NOPB equivalent, key selection criteria include LVDS receiver timing margin (≥400 ps skew margin at 66 MHz), TTL output drive capability (VOH ≥2.7 V at −0.4 mA), power-down current (<55 μA), and compatibility with TIA/EIA-644 LVDS standard.

Technical Context

The DS90CR286MTD/NOPB implements a PLL-based clock recovery architecture to reconstruct the embedded transmit clock from the LVDS clock pair, enabling synchronous sampling of serialized data without external reference. Its input stage accepts differential LVDS signals with 100 mV threshold and ±1.2 V common-mode range, while its 28 TTL outputs drive standard CMOS/LVTTL loads with 2.2–5.0 ns transition times.

It supports rising-edge data strobe timing synchronized to RxCLK OUT, provides configurable power-down mode via active-low PWR DWN pin, and maintains output states during loss of input clock. The device requires no external PLL components and uses internal termination-aware logic to manage inter-symbol interference and cable skew up to 150 ps.

Key Specifications

Pinout & Package

DS90CR286MTD/NOPB is housed in a 56-lead Low-Profile TSSOP package (Package Code DGG, R-PDSO-G56) with exposed thermal pad not connected internally. Pin layout is optimized for LVDS signal integrity: RxIN+/− pairs are grouped, ground pins (GND, PLL GND, LVDS GND) are distributed to minimize return-path inductance, and VCC rails are segregated per functional domain (TTL I/O, PLL, LVDS input).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS receiver applications.

Compared with DS90CR286MTD/NOPB, DS90CR286MTDX/NOPB offers identical performance in bulk packaging, while SN65LVDS32 lacks integrated clock recovery and cannot replace the full Channel Link receiver function-making DS90CR286MTD/NOPB the sole solution for embedded-clock serial links requiring 28-bit deserialization.

Availability

DS90CR286MTD/NOPB is available at Aetrix Electronics and suitable for flat-panel display interfaces, automotive infotainment systems, and medical imaging equipment requiring stable component supply with guaranteed long-term sourcing.

Supply support for DS90CR286MTD/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions.

The DS90CR286MTD/NOPB belongs to TI's Channel Link family, designed specifically for high-bandwidth, low-EMI parallel bus replacement in display, imaging, and industrial video applications.

FAQ

What is the maximum supported clock frequency for DS90CR286MTD/NOPB?

The DS90CR286MTD/NOPB is characterized for operation up to 66 MHz transmit clock frequency, delivering 1.848 Gbps aggregate data throughput. At this rate, it achieves 400 ps receiver skew margin, validated across −40°C to +85°C. Operation beyond 66 MHz is not specified and may result in timing violations or PLL unlock.

Does DS90CR286MTD/NOPB require external termination resistors?

Yes - DS90CR286MTD/NOPB requires a 100 Ω differential termination resistor across each LVDS input pair (RxIN+/− and RxCLK IN+/−) at the receiver side. This matches typical cable impedance and ensures signal integrity; no additional pull-up/pull-down resistors are needed, as the device uses current-mode input architecture.

How does the power-down mode affect DS90CR286MTD/NOPB outputs?

When PWR DWN is asserted low, DS90CR286MTD/NOPB drives all 28 RxOUT pins low and disables internal circuitry, reducing total supply current to <55 μA. The RxCLK OUT pin also stops toggling. Outputs remain in this forced-low state until PWR DWN is de-asserted and PLL lock is re-established (~10 ms).

Can DS90CR286MTD/NOPB interface directly with 5V logic systems?

No - DS90CR286MTD/NOPB is not 5V tolerant. Its RxOUT pins are LVCMOS/LVTTL compatible with 3.3 V supply only, and absolute maximum input voltage is VCC + 0.3 V (≤3.6 V). Direct connection to 5V systems risks permanent damage; level-shifting circuitry is required for interoperability.

What is the purpose of separate PLL VCC and LVDS VCC pins on DS90CR286MTD/NOPB?

DS90CR286MTD/NOPB uses segregated power domains to isolate noise-sensitive analog functions: PLL VCC supplies the phase-locked loop core for low-jitter clock recovery, while LVDS VCC powers the differential input receivers for optimal common-mode rejection. Separating these from TTL I/O VCC prevents digital switching noise from degrading timing accuracy or input sensitivity.