Texas Instruments DS90CR286MTDX/NOPB

Overview

DS90CR286MTDX/NOPB from Texas Instruments is a 28-bit LVDS receiver IC that converts four LVDS data streams and one LVDS clock stream back into 28-bit LVCMOS/LVTTL parallel data, operating at up to 66 MHz clock frequency with 1.848 Gbps aggregate throughput, 290 mV differential output swing, and −40°C to +85°C industrial temperature range - used in high-speed flat-panel display interconnects and embedded video links.

For engineers reviewing the DS90CR286MTDX/NOPB datasheet, DS90CR286MTDX/NOPB pinout, DS90CR286MTDX/NOPB application, or DS90CR286MTDX/NOPB equivalent, this page delivers verified technical context, exact pin functions, real-world timing margins, ESD-hardened LVDS interface behavior, and validated alternative options for Channel Link-based system design.

Technical Context

The DS90CR286MTDX/NOPB implements a PLL-based clock recovery architecture synchronized to an incoming LVDS clock pair (RxCLK IN±), reconstructing a clean TTL-level strobe (RxCLK OUT) aligned to recovered data edges. It supports rising-edge data sampling with 2.5–8.0 ns setup/hold windows depending on clock rate.

It accepts four differential LVDS data pairs (RxIN± ×4) and one differential LVDS clock pair, converting them into 28 single-ended TTL outputs (RxOUT[0:27]) with 2.2–5.0 ns CMOS/TTL transition times. Power-down mode forces all RxOUT pins low while drawing <55 μA total supply current.

Key Specifications

Pinout & Package

DS90CR286MTDX/NOPB uses a 56-lead TSSOP package (Package Code DGG, R-PDSO-G56) with exposed thermal pad, optimized for high-density PCB layouts and thermal dissipation in compact display interface modules.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserialization applications.

Compared with DS90CR286MTD/NOPB, DS90CR286MTDX/NOPB offers identical performance with optimized logistics for volume manufacturing; versus SN65LVDS32, it delivers integrated clock recovery and 28-bit parallel reconstruction - eliminating external timing management and reducing BOM count by 4× in display systems.

Availability

DS90CR286MTDX/NOPB is available at Aetrix Electronics and suitable for flat-panel display interfaces, automotive infotainment video links, and industrial camera sensor interfaces requiring stable component supply across extended product lifecycles.

Supply support for DS90CR286MTDX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions with broad industrial and automotive qualification.

DS90CR286MTDX/NOPB belongs to TI's Channel Link chipset family, designed specifically for high-reliability, low-EMI parallel data transport in display, imaging, and instrumentation systems where cable weight, connector size, and signal integrity are critical constraints.

FAQ

What is the primary function of the DS90CR286MTDX/NOPB in a Channel Link system?

The DS90CR286MTDX/NOPB is a 28-bit LVDS receiver IC that recovers clock and data from a DS90CR285 transmitter, converting four LVDS data streams and one LVDS clock stream into 28-bit LVCMOS/LVTTL parallel outputs. Its core function is deterministic deserialization with embedded PLL-based clock recovery - essential for maintaining timing integrity in display and imaging interfaces. DS90CR286MTDX/NOPB enables high-fidelity pixel transport without external clock distribution.

Does the DS90CR286MTDX/NOPB require external components for PLL operation?

No, the DS90CR286MTDX/NOPB integrates a fully self-contained PLL that locks to the incoming LVDS clock (RxCLK IN±) without requiring external capacitors, resistors, or crystal references. The PLL achieves lock within 10 ms and maintains stable phase alignment across −40°C to +85°C, eliminating bill-of-materials overhead and layout complexity. DS90CR286MTDX/NOPB's zero-external-component PLL is validated per SNLS130C datasheet Figure 15.

What is the maximum cable length supported by the DS90CR286MTDX/NOPB at 66 MHz?

The DS90CR286MTDX/NOPB supports up to 5 meters of Twin-Coax cable at 66 MHz, as demonstrated in TI application note AN-916. This capability relies on its 400 ps receiver skew margin (RSKM), 290 mV LVDS swing, and ±1.0 V common-mode tolerance - collectively enabling robust operation despite inter-pair skew, ground offset, and EMI. DS90CR286MTDX/NOPB's specification assumes proper 100 Ω termination and controlled-impedance routing per AN-1108 guidelines.

How does the power-down mode affect the outputs of the DS90CR286MTDX/NOPB?

When PWR DWN is asserted low, the DS90CR286MTDX/NOPB forces all 28 RxOUT pins to logic-low state and disables the internal PLL, reducing total supply current to <55 μA. Unlike TRI-STATE behavior, this is an active-drive low - ensuring defined signal levels on downstream logic during sleep. DS90CR286MTDX/NOPB exits power-down within 1 μs (RPDD) upon PWR DWN deassertion, restoring full functionality without reset sequencing.

Is the DS90CR286MTDX/NOPB compatible with 5V-tolerant logic interfaces?

No, the DS90CR286MTDX/NOPB is not 5V-tolerant. Its RxOUT outputs are LVCMOS/LVTTL compliant with VCC = 3.3 V nominal, specifying VOH ≥ 2.7 V and VOL ≤ 0.3 V under load - compatible only with 3.3 V logic families. Inputs (including PWR DWN) accept 0–3.6 V, but direct connection to 5V systems risks damage. DS90CR286MTDX/NOPB must be interfaced via level-shifting buffers or matched 3.3 V domain logic.