Texas Instruments DS90CR287MTD

Overview

DS90CR287MTD from Texas Instruments (formerly National Semiconductor) is a +3.3V LVDS transmitter IC that converts 28-bit parallel LVCMOS/LVTTL data into four LVDS data streams plus one LVDS clock stream, enabling high-speed point-to-point interconnect at up to 85 MHz clock rate and 2.38 Gbps aggregate throughput. It implements rising-edge data strobe timing, integrates a PLL with no external components, and targets EMI-sensitive display and imaging interfaces.

For engineers reviewing the DS90CR287MTD datasheet, DS90CR287MTD pinout, DS90CR287MTD application, or DS90CR287MTD equivalent, key selection criteria include its 56-pin TSSOP package, 28-bit parallel input mapping, LVDS differential output compliance per TIA/EIA-644, and power-down control via TTL-level PWR DOWN pin.

Technical Context

The DS90CR287MTD operates as the transmitter half of a bidirectional Channel Link chipset paired with DS90CR288A. Its internal PLL locks to a single-ended 3.3V TTL clock input (TxCLK IN), generating synchronized LVDS outputs for four data lanes and one clock lane - all referenced to dedicated LVDS VCC/GND and PLL VCC/GND supply domains.

It supports 20–85 MHz shift clock frequencies with 2.5 ns setup and 0 ns hold time on TxIN inputs, delivers 345 mV typical LVDS swing, maintains ±1V common-mode range around +1.2V, and achieves 297.5 MB/s bandwidth at 85 MHz while meeting TIA/EIA-644 LVDS electrical standards.

Key Specifications

Pinout & Package

DS90CR287MTD uses a 56-lead TSSOP package (NS package code MTD56), low-profile surface-mount construction with exposed thermal pad not electrically connected. Pin assignments are optimized for differential pair routing: TxOUT± and TxCLK OUT± grouped for impedance-controlled layout, separate VCC/GND domains for logic, PLL, and LVDS sections.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS transmitter applications.

Compared with DS90C387MTD, DS90CR287MTD offers identical functionality at lower cost for commercial-temperature applications, while SN65LVDS31DR requires additional clock management circuitry and does not support rising-edge strobe synchronization out-of-box.

Availability

DS90CR287MTD is available at Aetrix Electronics and suitable for display interface bridge, medical imaging data link, and industrial camera interface applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for DS90CR287MTD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments acquired National Semiconductor in 2011 and maintains full technical documentation, manufacturing, and support for legacy Channel Link products.

The DS90CR287MTD belongs to TI's high-speed interface portfolio designed specifically for EMI-critical, high-bandwidth parallel-to-serial conversion in display, imaging, and industrial vision systems.

FAQ

What is the maximum supported clock frequency for DS90CR287MTD?

The DS90CR287MTD supports a maximum shift clock frequency of 85 MHz, enabling 2.38 Gbps aggregate data throughput and 297.5 MB/s bandwidth. At this rate, each of the four LVDS data lanes carries 595 Mbps, with the fifth LVDS lane transmitting the synchronized clock. Operation above 85 MHz is not characterized or guaranteed.

Does DS90CR287MTD require external components for its PLL?

No, DS90CR287MTD integrates a fully self-contained PLL that requires no external capacitors, resistors, or crystals. The PLL locks to the incoming TxCLK IN signal and generates the precise phase-aligned LVDS clock and data timing internally - simplifying design and reducing bill-of-materials cost.

Can DS90CR287MTD interface directly with 5V logic systems?

No, DS90CR287MTD inputs are strictly 3.3V LVCMOS/LVTTL compatible and are not 5V tolerant. Applying 5V to TxIN or control pins risks permanent damage. System upgrades from legacy 5V Channel Link (e.g., DS90CR283) require level-shifting or supply voltage reduction to 3.3V.

What is the purpose of the separate PLL VCC and LVDS VCC pins on DS90CR287MTD?

The separate PLL VCC and LVDS VCC pins isolate noise-sensitive analog PLL circuitry and high-speed LVDS driver stages from digital logic supplies. This separation - combined with dedicated PLL GND and LVDS GND - minimizes supply-induced jitter and ensures stable clock recovery and clean differential output waveforms in DS90CR287MTD.

How does DS90CR287MTD handle power loss on the transmitter side?

When power is lost to the DS90CR287MTD transmitter, the receiver (e.g., DS90CR288A) detects loss of clock and halts toggling; its RxOUT data outputs retain their last valid state. This fail-safe behavior prevents spurious display artifacts or image corruption during transient power faults in systems using DS90CR287MTD.