Texas Instruments DS90CR287MTD/NOPB

Overview

DS90CR287MTD/NOPB from Texas Instruments (formerly National Semiconductor) is a +3.3V LVDS transmitter IC that converts 28-bit parallel LVCMOS/LVTTL data into four LVDS data streams plus one LVDS clock stream. It supports 20–85 MHz shift clock input, delivers 2.38 Gbps aggregate throughput at 85 MHz, and implements rising-edge data strobe timing for precise sampling in high-speed serial link applications such as flat-panel display interconnects.

For engineers reviewing the DS90CR287MTD/NOPB datasheet, DS90CR287MTD/NOPB pinout, DS90CR287MTD/NOPB application, or DS90CR287MTD/NOPB equivalent, key selection criteria include its 56-pin TSSOP package, 28-bit parallel-to-serial conversion, LVDS compliance per TIA/EIA-644, PLL-based clock recovery, and compatibility with DS90CR288A receiver for full Channel Link implementation.

Technical Context

The DS90CR287MTD/NOPB integrates a phase-locked loop (PLL) to generate synchronized LVDS clock output from TTL-level TxCLK IN, enabling deterministic timing alignment across all five differential outputs. Its internal data path maps 28 parallel inputs to four 7-bit LVDS lanes plus one dedicated clock lane, with pulse position tolerances of ±0.20 ns for Bit0 at 85 MHz.

It operates within 3.0–3.6 V supply range and −10°C to +70°C ambient temperature, features 345 mV typical LVDS differential swing, ±1 V common-mode input range centered at +1.2 V, and supports power-down mode via active-low PWR DOWN pin with <55 µA quiescent current.

Key Specifications

Pinout & Package

DS90CR287MTD/NOPB uses a 56-pin Thin Shrink Small Outline Package (TSSOP), JEDEC-compliant, with 0.5 mm lead pitch and exposed thermal pad (not electrically connected). Pin assignment follows National Semiconductor MTD56 mechanical outline.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS serializer applications.

Compared with DS90CR287MTD/NOPB, DS90UB925QSQ/NOPB adds protocol stack and security but sacrifices pin compatibility and clock embedding simplicity, while SN65LVDS31DR provides basic LVDS drive capability only-neither offers the integrated 28-bit Channel Link functionality, PLL synchronization, or TSSOP footprint of DS90CR287MTD/NOPB.

Availability

DS90CR287MTD/NOPB is available at Aetrix Electronics and suitable for industrial display interconnects, medical imaging subsystems, and avionics video distribution requiring stable component supply and long-term lifecycle support.

Supply support for DS90CR287MTD/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments acquired National Semiconductor in 2011 and maintains its legacy high-performance interface portfolio, including Channel Link technology.

DS90CR287MTD/NOPB belongs to TI's legacy Channel Link family, designed specifically for EMI-sensitive, high-bandwidth parallel-to-serial conversion in display and imaging systems where cable size and signal integrity are critical constraints.

FAQ

What is the primary function of the DS90CR287MTD/NOPB in a system?

The DS90CR287MTD/NOPB functions as a 28-bit parallel-to-LVDS serializer, converting LVCMOS/LVTTL data and control signals into four differential data streams plus one embedded clock stream. It enables high-speed, low-EMI transmission over compact cabling in applications like LCD display interfaces. The DS90CR287MTD/NOPB achieves this without external PLL components and supports clock rates from 20 MHz to 85 MHz.

Does the DS90CR287MTD/NOPB require external termination resistors?

No, the DS90CR287MTD/NOPB itself does not require external termination-it drives LVDS outputs actively. However, the receiving end (e.g., DS90CR288A) must be terminated with a 100 Ω resistor across each LVDS differential pair. This termination is mandatory for signal integrity and is specified in the DS90CR287MTD/NOPB application notes for proper impedance matching to the cable's differential characteristic impedance (90–120 Ω).

Can the DS90CR287MTD/NOPB operate with a 5V input interface?

No, the DS90CR287MTD/NOPB inputs are not 5V tolerant. Its TxIN and control pins accept only 3.3 V LVCMOS/LVTTL levels (VIH = 2.0 V min, VIL = 0.8 V max). Direct connection to 5V logic will damage the device. Level translation or voltage scaling is required when interfacing with legacy 5V systems, as documented in the Applications Information section of the DS90CR287MTD/NOPB datasheet.

What is the significance of the "rising edge data strobe" in the DS90CR287MTD/NOPB?

The DS90CR287MTD/NOPB uses the rising edge of the TxCLK IN signal as the sampling strobe for all 28 parallel inputs, enforcing strict timing discipline. At 85 MHz, this yields 2.5 ns setup time and zero hold time requirements-enabling tight integration with FPGA or ASIC output registers. This architecture ensures deterministic latency and simplifies timing closure in high-speed digital systems using the DS90CR287MTD/NOPB.

How does the DS90CR287MTD/NOPB handle power-down sequencing?

The DS90CR287MTD/NOPB enters low-power mode when the PWR DOWN pin is driven low, tri-stating all LVDS outputs and reducing supply current to under 55 µA. Power-down must be asserted before clock removal and held until clock re-stabilization to ensure PLL reset and lock. The DS90CR287MTD/NOPB also features separate VCC, PLL VCC, and LVDS VCC domains to allow staged power sequencing and optimized decoupling per functional block.