Texas Instruments DS90CR287MTDX/NOPB

Overview

DS90CR287MTDX/NOPB from Texas Instruments (formerly National Semiconductor) is a 28-bit LVDS transmitter IC that converts parallel LVCMOS/LVTTL data into four differential LVDS data streams plus one LVDS clock stream. It operates at up to 85 MHz shift clock frequency, delivers 2.38 Gbps aggregate throughput, and uses rising-edge data strobe timing. It is used in high-speed digital video interconnects such as flat-panel display interfaces.

For engineers reviewing the DS90CR287MTDX/NOPB datasheet, DS90CR287MTDX/NOPB pinout, DS90CR287MTDX/NOPB application, or DS90CR287MTDX/NOPB equivalent, key selection criteria include 28-bit parallel-to-serial conversion capability, TSSOP-56 package compatibility, 3.3V supply operation, LVDS compliance per TIA/EIA-644, and precise pulse positioning for skew-tolerant cable transmission.

Technical Context

The DS90CR287MTDX/NOPB implements a PLL-based clock recovery and serialization architecture optimized for point-to-point 28-bit data links. It accepts a single-ended 3.3V TTL clock input (TxCLK IN), generates a phase-aligned LVDS clock output (TxCLK OUT±), and maps 28 parallel inputs across four LVDS data pairs with deterministic pulse positioning (e.g., TPPos0 = −0.20 to +0.20 ns at 85 MHz).

It supports 20–85 MHz shift clock range with 2.5 ns setup / 0 ns hold time on TxIN inputs, ±1V common-mode input range centered at +1.2V, and integrated power-down control (PWR DOWN) enabling TRI-STATE outputs with <55 µA quiescent current. Its LVDS drivers deliver 250–450 mV differential swing with 345 mV typical, meeting EMI-sensitive system requirements.

Key Specifications

Pinout & Package

DS90CR287MTDX/NOPB is housed in a 56-lead molded thin shrink small outline package (TSSOP), NS package number MTD56, with 0.5 mm lead pitch and exposed thermal pad (not electrically connected). Pin layout is optimized for differential pair routing: TxOUT± and TxCLK OUT± pins are grouped in adjacent pairs to minimize skew.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS serializer applications.

Compared with DS90CR287MTDX/NOPB, DS90CR287MTD offers identical electrical performance but lacks explicit Pb-free certification, while SN65LVDS328 adds spread-spectrum and higher ESD rating at the cost of slightly increased propagation delay and different power-down timing.

Availability

DS90CR287MTDX/NOPB is available at Aetrix Electronics and suitable for display interface design, industrial camera systems, and medical imaging equipment requiring stable component supply and long-term obsolescence management.

Supply support for DS90CR287MTDX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments acquired National Semiconductor in 2011 and maintains legacy product support, datasheets, and cross-reference tools for discontinued National parts.

The DS90CR287MTDX/NOPB belongs to TI's Channel Link serializer family, designed specifically for high-bandwidth, low-EMI parallel-to-LVDS conversion in display, imaging, and instrumentation applications.

FAQ

What is the maximum supported clock frequency for DS90CR287MTDX/NOPB?

The DS90CR287MTDX/NOPB supports a maximum shift clock frequency of 85 MHz, enabling a total data throughput of 2.38 Gbps across its four LVDS data lanes and one LVDS clock lane. At this rate, it achieves 297.5 MB/s bandwidth, sufficient for UXGA (1600×1200) display interfaces running at 60 Hz with blanking intervals. Operation above 85 MHz is not characterized or guaranteed.

Does DS90CR287MTDX/NOPB require external components for PLL operation?

No, DS90CR287MTDX/NOPB integrates a fully self-contained PLL that requires no external capacitors, resistors, or crystals. The PLL locks to the incoming TxCLK IN signal within 10 ms and maintains stable operation across the 20–85 MHz input clock range. This eliminates tuning complexity and reduces PCB area versus discrete PLL solutions.

Can DS90CR287MTDX/NOPB interface directly with 5V logic systems?

No, DS90CR287MTDX/NOPB inputs are strictly 3.3V LVCMOS/LVTTL compatible and are not 5V tolerant. Applying 5V to TxIN or control pins may damage the device. To interface with 5V systems, level-shifting circuitry (e.g., TXB0304 or discrete MOSFET translators) is required on all input signals, including TxCLK IN and PWR DOWN.

What is the recommended termination for DS90CR287MTDX/NOPB LVDS outputs?

DS90CR287MTDX/NOPB LVDS outputs require 100 Ω differential termination at the receiver end (e.g., DS90CR288A inputs), placed as close as possible to the receiver pins. The termination resistor value should match the characteristic impedance of the interconnect-typically 90–120 Ω for Twin-Coax or shielded twisted-pair cables. No AC coupling or biasing resistors are needed, as DS90CR287MTDX/NOPB drives true LVDS levels.

How does DS90CR287MTDX/NOPB handle power-down sequencing?

DS90CR287MTDX/NOPB enters low-power mode when PWR DOWN is pulled low, tri-stating all LVDS outputs and reducing supply current to ≤55 µA. The input clock (TxCLK IN) must be active before releasing PWR DOWN; if the clock stops during operation, PWR DOWN must be asserted first to prevent PLL unlock. Power-up sequencing requires VCC ≥2V before outputs activate, with full toggling beginning 10 ms after VCC reaches 3V and PWR DOWN is high.