Texas Instruments DS90CR287SLC/NOPB

Overview

DS90CR287SLC/NOPB from Texas Instruments (formerly National Semiconductor) is a +3.3V LVDS transmitter IC that converts 28-bit parallel LVCMOS/LVTTL data into four differential LVDS data streams plus one LVDS clock stream. It supports 20–85 MHz shift clock input, delivers 2.38 Gbps aggregate throughput at 85 MHz, and operates in industrial temperature range (−10°C to +70°C). It is used in high-speed digital video interconnects such as flat-panel display interfaces.

For engineers reviewing the DS90CR287SLC/NOPB datasheet, DS90CR287SLC/NOPB pinout, DS90CR287SLC/NOPB application, or DS90CR287SLC/NOPB equivalent, key selection criteria include LVDS channel count (4 data + 1 clock), TSSOP-56 package compatibility, 85 MHz maximum clock rate, 28-bit parallel interface timing, and compliance with TIA/EIA-644 LVDS standard.

Technical Context

The DS90CR287SLC/NOPB implements a rising-edge data strobe architecture where TxCLK IN's rising edge samples all 28 input bits simultaneously. Its internal PLL generates a synchronized transmit clock without external components and maintains lock across 20–85 MHz input frequencies.

It drives five LVDS differential pairs: four for serialized data (TxOUT± ×4) and one for the embedded clock (TxCLK OUT±). The device features programmable power-down mode (PWR DOWN active-low), ±1 V common-mode input range centered at +1.2 V, and 345 mV typical differential output swing optimized for low EMI.

Key Specifications

Pinout & Package

DS90CR287SLC/NOPB is housed in a 56-lead TSSOP package (NS package code MTD56), measuring 12.5 mm × 6.1 mm × 1.2 mm, with 0.5 mm lead pitch. It requires standard surface-mount reflow and supports automated optical inspection (AOI).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS serializer applications.

Compared with DS90CR287SLC/NOPB, DS90CR287MTD offers identical performance with non-RoHS labeling, while SN65LVDS328 extends temperature range and drive capability at the cost of higher power and slightly larger footprint - making it preferable for harsh-environment or long-cable deployments.

Availability

DS90CR287SLC/NOPB is available at Aetrix Electronics and suitable for flat-panel display interfaces, industrial camera links, medical imaging backplanes, and avionics video distribution requiring stable component supply and long-term lifecycle support.

Supply support for DS90CR287SLC/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments acquired National Semiconductor in 2011 and maintains full technical and manufacturing continuity for legacy Channel Link products.

The DS90CR287SLC/NOPB belongs to TI's high-speed interface portfolio, designed specifically for EMI-sensitive parallel-to-serial conversion in display, imaging, and real-time video systems.

FAQ

What is the maximum supported clock frequency for DS90CR287SLC/NOPB?

The DS90CR287SLC/NOPB supports a maximum shift clock frequency of 85 MHz. At this rate, it achieves 595 Mbps per LVDS data channel and 2.38 Gbps aggregate throughput. Operation above 85 MHz is not guaranteed and violates the device's AC timing specifications, including setup/hold margins and pulse position tolerances.

Does DS90CR287SLC/NOPB require external components for its PLL?

No, DS90CR287SLC/NOPB integrates a fully self-contained PLL that requires no external capacitors, resistors, or crystals. The PLL locks automatically to the incoming TxCLK IN signal across its 20–85 MHz range and maintains stable phase alignment without user intervention or calibration.

Is DS90CR287SLC/NOPB compatible with 5 V logic inputs?

No, DS90CR287SLC/NOPB inputs are strictly 3.3 V LVCMOS/LVTTL compatible and are not 5 V tolerant. Applying 5 V to any input pin - including TxIN, TxCLK IN, or PWR DOWN - exceeds absolute maximum ratings and may cause permanent damage. Level translation is required for interfacing with 5 V systems.

What is the purpose of separate VCC, PLL VCC, and LVDS VCC pins on DS90CR287SLC/NOPB?

These dedicated supply pins isolate noise-sensitive circuit blocks: VCC powers digital I/O, PLL VCC supplies the phase-locked loop core, and LVDS VCC drives the differential output stage. This separation prevents switching noise from logic transitions from modulating the PLL or distorting LVDS output symmetry - essential for maintaining jitter below 2 ns cycle-to-cycle.

How does DS90CR287SLC/NOPB handle power-down sequencing?

DS90CR287SLC/NOPB enters low-power mode when PWR DOWN is pulled low, tri-stating all LVDS outputs and reducing supply current to ≤55 µA. The input clock (TxCLK IN) must remain active during power-down assertion; removing the clock before asserting PWR DOWN risks undefined PLL state and extended lock time upon re-enable.