Texas Instruments DS90CR288AMTD/NOPB
- Part No.:
- DS90CR288AMTD/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 56-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
DS90CR288AMTD/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 56TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:753
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Product details
Overview
DS90CR288AMTD/NOPB from Texas Instruments (formerly National Semiconductor) is a 28-bit LVDS receiver IC for Channel Link serial interface systems. It converts four LVDS data streams and one LVDS clock into 28-bit LVCMOS/LVTTL parallel data with 50% duty cycle output clock, supports up to 85 MHz input clock frequency, delivers 2.38 Gbps aggregate throughput, and operates at +3.3 V supply. It is used in high-speed digital video interconnects between graphics controllers and flat-panel displays.
For engineers reviewing the DS90CR288AMTD/NOPB datasheet, DS90CR288AMTD/NOPB pinout, DS90CR288AMTD/NOPB application, or DS90CR288AMTD/NOPB equivalent, key selection criteria include LVDS receiver skew margin (290 ps at 85 MHz), RxCLK OUT jitter tolerance, power-down behavior (outputs forced low), and compatibility with DS90CR287 transmitter in 56-lead TSSOP package.
Technical Context
The DS90CR288AMTD/NOPB implements a PLL-based clock recovery architecture synchronized to the incoming LVDS clock pair (RxCLK IN±), enabling deterministic sampling of four differential data lanes. Its internal strobe positioning (RSPos0–RSPos6) defines precise bit-aligned sampling windows relative to the recovered clock edge.
It features failsafe biasing for floating/terminated inputs (guaranteeing HIGH outputs), supports ±1 V common-mode range around +1.2 V, and requires external 100 Ω differential termination on each LVDS input pair. Power-down mode asserts low-level TTL outputs and reduces supply current to 140–400 µA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.0–3.6 V - Ensures stable operation across industrial temperature range (−10°C to +70°C). |
| Data Rate per Lane | 595 Mbps - Enables 28-bit parallel data transmission over four LVDS pairs at 85 MHz clock. |
| Aggregate Throughput | 2.38 Gbps - Supports high-bandwidth video transport (e.g., UXGA @ 60 Hz with embedded sync). |
| RxCLK OUT Duty Cycle | 4–6.5 ns high time / 3.5–6 ns low time - Provides balanced TTL clock for synchronous latch timing. |
| Skew Margin (RSKM) | 290 ps - Specifies maximum allowable inter-pair cable skew while maintaining valid data sampling window. |
| Power-Down Current | 140–400 µA - Minimizes standby power when system enters low-power state without disabling supply rails. |
| LVDS Input Threshold | ±100 mV differential - Defines robust noise immunity against common-mode interference on long cables. |
Pinout & Package
DS90CR288AMTD/NOPB is housed in a 56-lead TSSOP package (NS MTD56, JEDEC MO-153), 12.5 mm × 6.1 mm × 1.2 mm, with 0.5 mm lead pitch. Thermal pad not present; standard surface-mount reflow compatible.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RxIN+ / RxIN− (×4) | Differential LVDS data inputs | Accept serialized 28-bit data across four matched pairs; require 100 Ω termination at receiver end. |
| RxCLK IN+ / RxCLK IN− | Differential LVDS clock input | Carries recovered clock from DS90CR287; drives internal PLL for data sampling synchronization. |
| RxOUT[0:27] | LVCMOS/LVTTL parallel data outputs | 28-bit TTL-compatible outputs; all driven LOW during PWR DOWN assertion. |
| RxCLK OUT | TTL clock output | Rising-edge strobe synchronized to recovered clock; 50% duty cycle enables reliable latch timing. |
| PWR DOWN | Active-low control input | Forces RxOUT to logic LOW and reduces ICC to µA range; no hold time required before clock re-enable. |
| VCC (×4) | +3.3 V supply for TTL I/O | Must be decoupled with 0.1 µF / 0.01 µF / 0.001 µF capacitors near each pin for noise suppression. |
| LVDS VCC (×1) | +3.3 V supply for LVDS input receivers | Separate rail minimizes coupling between analog LVDS front-end and digital output stage. |
| PLL VCC (×1) | +3.3 V supply for PLL core | Highest priority for decoupling; noise here directly impacts clock jitter and data eye integrity. |
Key Features
| Feature | Design Value |
|---|---|
| Failsafe input biasing | Guarantees HIGH output state on floating or terminated LVDS inputs - eliminates undefined display artifacts during hot-plug or cable disconnect. |
| 290 ps skew margin (RSKM) | Enables use of cost-effective flat ribbon or flex cable up to ~2 m length at 85 MHz without signal integrity loss. |
| Low-jitter PLL clock recovery | Supports <150 ps cycle-to-cycle jitter on TxCLK IN - critical for maintaining data eye opening across long interconnects. |
| 100 Ω differential termination support | Eliminates need for external bias networks; matches standard LVDS cable impedance and simplifies PCB layout. |
| Independent power domains | VCC (TTL I/O), LVDS VCC (receiver front-end), and PLL VCC (clock synthesis) allow targeted decoupling and noise isolation. |
Applications
| LCD Panel Interface | Medical Imaging Display Link |
|---|---|
|
Use Scenario: High-resolution TFT-LCD module connected to GPU via flexible flat cable inside diagnostic ultrasound or MRI console. IC Role / Device Role / Timing Role: DS90CR288AMTD/NOPB recovers clock and deserializes 28-bit RGB+sync data from DS90CR287 transmitter for pixel clock-aligned display rendering. Use Value: Replaces 28-wire parallel TTL bus with 10-wire LVDS (5 pairs), reducing EMI by >30 dB and enabling longer cable runs (>1.5 m) without signal degradation. |
Use Scenario: Real-time DICOM image streaming from acquisition board to high-brightness surgical monitor in OR environment. IC Role / Device Role / Timing Role: DS90CR288AMTD/NOPB acts as timing-critical LVDS receiver ensuring sub-nanosecond clock/data alignment for zero-frame-drop video playback. Use Value: 290 ps skew margin accommodates cable assembly tolerances in certified medical harnesses, eliminating field-reported image tearing. |
| Industrial HMI Video Backplane | Avionics Display Data Bus |
|
Use Scenario: Ruggedized touch HMI in factory automation panel using twisted-pair wiring between controller and display unit. IC Role / Device Role / Timing Role: DS90CR288AMTD/NOPB receives serialized video and reconstructs parallel interface for FPGA-based display controller with programmable timing. Use Value: ±1 V common-mode range handles ground potential differences between isolated chassis sections, preventing communication failure in noisy plant environments. |
Use Scenario: Multi-function display (MFD) in commercial aircraft cockpit receiving synthetic vision data from flight management system. IC Role / Device Role / Timing Role: DS90CR288AMTD/NOPB provides fail-safe LVDS reception: floating inputs default to HIGH, preserving last valid frame during transient power dips. Use Value: Meets DO-160E Section 20 lightning-induced transient immunity requirements due to robust common-mode noise rejection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS deserializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN65LVDS32 | Single-channel LVDS receiver (not 28-bit); no integrated PLL or clock recovery; requires external clock. | Suitable only for point-to-point links with separate clock distribution - cannot replace DS90CR288AMTD/NOPB in Channel Link systems. | Select only if redesigning interface to use separate clock routing and lower channel count. |
| DS90CF564MTD | 24-bit LVDS receiver with 165 MHz max clock; different pinout; supports only 4 data lanes + clock (no 28-bit mapping). | Designed for DVI source-side deserialization; lacks RSPos timing calibration and failsafe biasing of DS90CR288AMTD/NOPB. | Use only for DVI-compliant video paths requiring higher bandwidth but accepting reduced feature set. |
Compared with SN65LVDS32 and DS90CF564MTD, DS90CR288AMTD/NOPB uniquely integrates full 28-bit deserialization, PLL-based clock recovery, and failsafe biasing in a single TSSOP package - making it irreplaceable in legacy Channel Link display interfaces without board redesign.
Availability
DS90CR288AMTD/NOPB is available at Aetrix Electronics and suitable for LCD panel interface, medical imaging display link, industrial HMI video backplane, avionics display data bus, and test equipment video capture requiring stable component supply and long-term lifecycle support.
Supply support for DS90CR288AMTD/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments acquired National Semiconductor in 2011 and maintains full technical documentation, manufacturing, and support for legacy Channel Link products including DS90CR288AMTD/NOPB.
The DS90CR288AMTD/NOPB belongs to TI's high-speed interface portfolio designed specifically for EMI-sensitive, high-bandwidth parallel-to-serial conversion in display and imaging subsystems.
FAQ
What is the function of the PWR DOWN pin on DS90CR288AMTD/NOPB?
The PWR DOWN pin on DS90CR288AMTD/NOPB is an active-low control input that forces all 28 RxOUT data outputs to logic LOW and reduces supply current to 140–400 µA. When asserted, it disables the internal PLL and places LVDS receivers in high-impedance state - essential for power gating in portable or thermally constrained systems. DS90CR288AMTD/NOPB resumes normal operation within 1 µs after PWR DOWN is de-asserted and clock is stable.
Does DS90CR288AMTD/NOPB require external termination resistors?
Yes, DS90CR288AMTD/NOPB requires external 100 Ω differential termination resistors across each of the five LVDS input pairs (four data + one clock). The device itself does not integrate termination; this resistor must be placed as close as possible to the RxIN+/− and RxCLK IN+/− pins to minimize stub length and preserve signal integrity. DS90CR288AMTD/NOPB supports termination values from 90 Ω to 120 Ω to match actual cable characteristic impedance.
Can DS90CR288AMTD/NOPB operate with a 5 V supply?
No, DS90CR288AMTD/NOPB is strictly a +3.3 V device with absolute maximum VCC of +4.0 V. Its LVCMOS/LVTTL inputs are not 5 V tolerant - applying 5 V to RxCLK OUT, RxOUT, or any control pin will exceed absolute maximum ratings and may cause permanent damage. DS90CR288AMTD/NOPB must be powered from a regulated 3.0–3.6 V supply, and interfaced only with 3.3 V logic families.
How does DS90CR288AMTD/NOPB handle floating LVDS inputs?
DS90CR288AMTD/NOPB includes internal failsafe bias circuitry that pulls floating or unterminated LVDS inputs to a defined HIGH state. If only the data pairs float while RxCLK IN± remains active, all 28 RxOUT bits go HIGH. If both data and clock inputs float, RxOUT retains the last valid latched state. This prevents undefined display glitches during cable disconnection or hot-swap events - a critical reliability feature confirmed in DS90CR288AMTD/NOPB's Applications Information section.
What is the minimum recommended bypass capacitance for DS90CR288AMTD/NOPB?
Texas Instruments recommends three parallel surface-mount ceramic capacitors per supply domain: 0.1 µF, 0.01 µF, and 0.001 µF, placed between each VCC pin and ground plane. PLL VCC has highest priority for decoupling; LVDS VCC is secondary; logic VCC is tertiary. Each capacitor must have its own dedicated via to the ground plane - this configuration suppresses switching noise across 10 kHz–1 GHz and ensures DS90CR288AMTD/NOPB achieves specified 290 ps skew margin and low-jitter performance.
DS90CR288AMTD/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 56-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 56-TSSOP
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90CR288AMTD/NOPB FAQ
1.How can I place an order for DS90CR288AMTD/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CR288AMTD/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CR288AMTD/NOPB reliable?
The price and inventory of DS90CR288AMTD/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CR288AMTD/NOPB is usually 5 days.
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DS90CR288AMTD/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CR288AMTD/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CR288AMTD/NOPB?
For technical support, including DS90CR288AMTD/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CR288AMTD/NOPB requirements.
6.How does Aetrix verify that DS90CR288AMTD/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90CR288AMTD/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CR288AMTD/NOPB meets industry standards.
7.What is the process for return or replacement of DS90CR288AMTD/NOPB?
All DS90CR288AMTD/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90CR288AMTD/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CR288AMTD/NOPB part is unused and in its original packaging.
Return procedure for DS90CR288AMTD/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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