Texas Instruments DS90CR288AMTDX

Overview

DS90CR288AMTDX from Texas Instruments (formerly National Semiconductor) is a 28-bit LVDS receiver IC for high-speed serial data de-serialization in +3.3V systems. It recovers 28-bit parallel LVCMOS/LVTTL data from four LVDS data lanes and one LVDS clock lane, supporting up to 85 MHz input clock frequency and delivering 2.38 Gbps aggregate throughput. It serves as the receiver half of the DS90CR287/DS90CR288A Channel Link chipset in flat-panel display interconnects.

For engineers reviewing the DS90CR288AMTDX datasheet, DS90CR288AMTDX pinout, DS90CR288AMTDX application, or DS90CR288AMTDX equivalent, key selection criteria include its 56-pin TSSOP package, 85 MHz maximum clock rate, 297.5 MB/s bandwidth, ±1 V common-mode input range, and compatibility with TIA/EIA-644 LVDS standard - all critical for EMI-sensitive display interface designs.

Technical Context

The DS90CR288AMTDX implements a PLL-based clock recovery architecture to reconstruct a clean 85 MHz TTL clock (RxCLK OUT) from the incoming LVDS clock pair (RxCLK IN±), enabling synchronous sampling of serialized data. Its internal data sampling window is defined by strobe positions RSPos0–RSPos6, with skew margin (RSKM) of 290 ps at 85 MHz to accommodate cable skew and inter-symbol interference.

It features dedicated power domains: VCC for TTL outputs (4 pins), PLL VCC and PLL GND for phase-locked loop circuitry, LVDS VCC and LVDS GND for differential input receivers, and five ground pins for TTL output return paths. Power-down mode (PWR DOWN = low) forces RxOUT to logic low and reduces supply current to ≤400 µA.

Key Specifications

Pinout & Package

DS90CR288AMTDX is housed in a 56-lead TSSOP package (NS package code MTD56), measuring 12.5 mm × 6.1 mm × 1.2 mm, with 0.5 mm lead pitch and exposed thermal pad (not electrically connected). The package supports standard reflow soldering per JEDEC J-STD-020.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with SN65LVDS32 and DS90CF564MTD, DS90CR288AMTDX uniquely delivers 28-bit width, integrated PLL-based clock recovery, and guaranteed 290 ps skew margin at 85 MHz - making it irreplaceable in legacy Channel Link display interfaces requiring exact functional and timing equivalence.

Availability

DS90CR288AMTDX is available at Aetrix Electronics and suitable for flat-panel display interconnects, industrial HMI video interfaces, medical imaging display links, and automotive infotainment video bridges requiring stable component supply and long-term lifecycle support.

Supply support for DS90CR288AMTDX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments acquired National Semiconductor in 2011 and maintains full technical and manufacturing continuity for legacy interface products including the Channel Link family.

The DS90CR288AMTDX belongs to TI's high-speed interface product line, engineered specifically for EMI-critical parallel-to-serial video bridging in display subsystems where cable size, power, and signal integrity are constrained.

FAQ

What is the maximum supported clock frequency for DS90CR288AMTDX?

The DS90CR288AMTDX supports a maximum transmit clock frequency of 85 MHz, enabling a data throughput of 2.38 Gbps (297.5 MB/s). This is confirmed in the Absolute Maximum Ratings and Electrical Characteristics tables, where AC timing parameters (e.g., RSPos0–RSPos6, RCCD) are specified explicitly at f = 85 MHz. Operating beyond this frequency violates guaranteed timing margins and may cause data corruption.

Does DS90CR288AMTDX require external termination resistors?

Yes, DS90CR288AMTDX requires a 100 Ω termination resistor across each LVDS differential pair (RxIN+/−, RxCLK IN+/−) at the receiver input. The datasheet specifies this in the Applications Information section and Figure 17, noting that the resistor value should match the cable's differential impedance (typically 90–120 Ω). No pull-up or pull-down resistors are needed - the device includes internal failsafe biasing.

How does the PWR DOWN pin function on DS90CR288AMTDX?

When PWR DOWN is asserted low, DS90CR288AMTDX forces all 28 RxOUT pins to logic LOW and disables the internal PLL, reducing supply current to ≤400 µA. Unlike TRI-STATE behavior, outputs remain actively driven low - preventing floating states in display timing circuits. This is distinct from the transmitter's PWR DOWN, which places outputs in high-impedance mode.

Is DS90CR288AMTDX pin-compatible with the older DS90CR284 receiver?

No, DS90CR288AMTDX is not pin-compatible with DS90CR284. While both are Channel Link receivers, DS90CR284 is a 5V device in a different package (SOIC-28), whereas DS90CR288AMTDX is a +3.3V device in 56-pin TSSOP (MTD56) with separate power domains (PLL VCC, LVDS VCC) and additional ground pins. The pin count, layout, and power architecture differ fundamentally.

What is the purpose of the separate PLL VCC and LVDS VCC supplies on DS90CR288AMTDX?

The separate PLL VCC and LVDS VCC supplies isolate noise-sensitive analog circuitry (PLL and LVDS receivers) from digital switching noise generated by the TTL output drivers. This separation improves jitter performance and common-mode rejection - critical for maintaining the 290 ps skew margin at 85 MHz. The datasheet mandates individual decoupling for each domain, with PLL VCC receiving highest-priority filtering.