Texas Instruments DS90CR288AMTDX/NOPB

Overview

DS90CR288AMTDX/NOPB from Texas Instruments (formerly National Semiconductor) is a 28-bit LVDS receiver IC for high-speed serial data deserialization in Channel Link interfaces. It converts four LVDS data streams and one LVDS clock into 28-bit LVCMOS/LVTTL parallel output, supports up to 85 MHz clock frequency, delivers 2.38 Gbps aggregate throughput, and operates at +3.3 V supply. It is used in flat-panel display interconnects between graphics controllers and timing controllers.

For engineers reviewing the DS90CR288AMTDX/NOPB datasheet, DS90CR288AMTDX/NOPB pinout, DS90CR288AMTDX/NOPB application, or DS90CR288AMTDX/NOPB equivalent, key selection criteria include LVDS input compatibility, 56-pin TSSOP package constraints, 85 MHz maximum clock rate, 297.5 MB/s bandwidth requirement, and power-down behavior with low-level assertion.

Technical Context

The DS90CR288AMTDX/NOPB implements a PLL-based clock recovery architecture synchronized to an incoming LVDS clock pair (RxCLK IN±), enabling deterministic sampling of four LVDS data pairs. Its internal strobe positioning (RSPos0–RSPos6) defines precise bit-aligned sampling windows relative to the recovered clock edge.

It features failsafe biasing for floating/terminated LVDS inputs, guarantees TTL-level outputs with 50% duty cycle on RxCLK OUT, and supports skew margin ≥290 ps at 85 MHz - accommodating cable skew, inter-symbol interference, and source clock jitter ≤150 ps.

Key Specifications

Pinout & Package

DS90CR288AMTDX/NOPB uses a 56-lead TSSOP package (NS MTD56, JEDEC MO-153), low-profile (1.2 mm max height), with exposed thermal pad not electrically connected. Pin layout separates LVDS input, TTL output, power, and ground domains to minimize coupling.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with SN65LVDS32 and DS90CF564MTD, DS90CR288AMTDX/NOPB uniquely integrates full Channel Link protocol compliance - including PLL-based clock recovery, 28-bit parallel TTL output, and failsafe biasing - making it irreplaceable in legacy or cost-optimized display interconnects requiring drop-in compatibility with DS90CR287.

Availability

DS90CR288AMTDX/NOPB is available at Aetrix Electronics and suitable for LCD timing controller interfaces, medical imaging displays, industrial HMI backplanes, and avionics display data distribution requiring stable component supply across extended product lifecycles.

Supply support for DS90CR288AMTDX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments acquired National Semiconductor in 2011 and maintains its high-performance interface portfolio, emphasizing robustness, signal integrity, and long-term industrial support.

The DS90CR288AMTDX/NOPB belongs to TI's Channel Link serializer/deserializer family, designed specifically for EMI-resistant, high-bandwidth parallel-to-serial conversion in display, imaging, and real-time video systems.

FAQ

What is the maximum supported clock frequency for DS90CR288AMTDX/NOPB?

The DS90CR288AMTDX/NOPB supports a maximum transmit clock frequency of 85 MHz, enabling 2.38 Gbps aggregate throughput and 297.5 MB/s bandwidth. This is validated across the full operating temperature range (−10°C to +70°C) and supply voltage (3.0–3.6 V). Exceeding 85 MHz violates AC timing specifications including RSKM and pulse position tolerances.

Does DS90CR288AMTDX/NOPB require external termination resistors?

Yes - DS90CR288AMTDX/NOPB requires a 100 Ω differential termination resistor across each LVDS input pair (RxIN+/− and RxCLK IN+/−) placed as close as possible to the input pins. The device does not integrate termination; omission causes signal reflections, degraded eye diagrams, and failure to meet the ≥290 ps skew margin specification at 85 MHz.

How does the failsafe feature behave on DS90CR288AMTDX/NOPB when inputs are floating?

When LVDS inputs are floating or terminated without signal, DS90CR288AMTDX/NOPB's internal failsafe biasing pulls receiver outputs HIGH. If RxCLK IN± is also floating, RxOUT retains its last valid state; if a clock is present, all 28 bits go HIGH. This prevents undefined display states in hot-plug or cable-fault scenarios - a critical reliability feature for medical and industrial displays.

Can DS90CR288AMTDX/NOPB be used with the older 5V Channel Link transmitter DS90CR283?

No - DS90CR288AMTDX/NOPB is a +3.3 V device and is not 5V-tolerant on any input. It is backward compatible only with the +3.3 V DS90CR287 transmitter, not the 5V DS90CR283. Interfacing with DS90CR283 would violate absolute maximum ratings (e.g., VIH > VCC + 0.3 V) and risk permanent damage to DS90CR288AMTDX/NOPB inputs.

What is the power-down behavior of DS90CR288AMTDX/NOPB?

When PWR DOWN is asserted low, DS90CR288AMTDX/NOPB disables its PLL, stops toggling RxCLK OUT, and forces all 28 RxOUT pins to logic LOW. Supply current drops to 140–400 µA. Outputs remain LOW until PWR DOWN is deasserted and the PLL relocks - ensuring predictable, glitch-free state transitions during sleep/wake cycles in portable displays.