My Inquiry
My Account
Texas Instruments DS90CR288ASLC/NOPB
- Part No.:
- DS90CR288ASLC/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 64-LFBGA
- Datasheet:
-
DS90CR288ASLC/NOPB.pdf
- Description:
- IC INTFACE SPECIALIZED 64NFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:4,948
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90CR288ASLC/NOPB from Texas Instruments (formerly National Semiconductor) is a 28-bit LVDS receiver IC for Channel Link serial interface systems. It converts four LVDS data streams and one LVDS clock into 28-bit LVCMOS/LVTTL parallel data with 50% duty cycle output clock, supporting up to 85 MHz input clock frequency and 2.38 Gbps aggregate throughput. It operates at +3.3 V supply and is used in high-speed digital video interconnects between FPGAs and display timing controllers.
For engineers reviewing the DS90CR288ASLC/NOPB datasheet, DS90CR288ASLC/NOPB pinout, DS90CR288ASLC/NOPB application, or DS90CR288ASLC/NOPB equivalent, key selection criteria include LVDS receiver skew margin (290 ps at 85 MHz), 100 mV differential input threshold, ±1 V common-mode input range, and TSSOP-56 package compatibility with legacy Channel Link designs.
Technical Context
The DS90CR288ASLC/NOPB implements a PLL-based clock recovery architecture that locks to the incoming LVDS clock (RxCLK IN±) and regenerates a clean TTL-level strobe (RxCLK OUT) aligned to recovered data. Its internal data sampling window (RSPOS) is defined across seven bit positions with precise timing margins (e.g., RSPos0 = 0.49–1.19 ns at 85 MHz).
It supports fail-safe biasing for floating or terminated LVDS inputs, ensuring stable HIGH outputs when no valid signal is present. The receiver accepts standard TIA/EIA-644-compliant LVDS inputs with 100 Ω differential termination and provides 28 CMOS/TTL outputs with 1.8–3.5 ns transition times and 3.5 ns setup/hold relative to RxCLK OUT.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.0–3.6 V - Enables direct integration into 3.3 V logic domains without level-shifting. |
| Data Width | 28-bit parallel LVCMOS/LVTTL output - Matches standard RGB+sync video bus widths for display interfaces. |
| Max Clock Frequency | 85 MHz - Supports pixel rates up to ~297.5 MB/s, sufficient for WXGA (1280×800) @ 60 Hz with embedded sync. |
| Differential Input Threshold | ±100 mV - Provides robust noise immunity against common-mode disturbances in cable transmission. |
| Skew Margin | 290 ps - Specifies maximum allowable inter-pair cable skew at 85 MHz to maintain valid data sampling window. |
| Power Consumption | 96–135 mA at 85 MHz - Enables thermal management in dense PCB layouts with multiple Channel Link receivers. |
| Common-Mode Range | 0–2.4 V - Accommodates ground potential differences up to ±1.0 V between transmitter and receiver boards. |
Pinout & Package
DS90CR288ASLC/NOPB is housed in a low-profile 56-lead TSSOP package (NS package code MTD56), compatible with standard surface-mount assembly processes and legacy Channel Link layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RxIN+ / RxIN− | LVDS differential data inputs (4 pairs) | Accept serialized 28-bit data over five LVDS lanes (four data + one clock); require 100 Ω differential termination at receiver end. |
| RxCLK IN+ / RxCLK IN− | LVDS differential clock input | Carries recovered clock from DS90CR287 transmitter; drives internal PLL for data sampling alignment. |
| RxOUT[0:27] | LVCMOS/LVTTL parallel data outputs | Deliver 28-bit parallel data synchronized to rising edge of RxCLK OUT; drive standard 3.3 V logic loads. |
| RxCLK OUT | TTL-level clock output | Regenerated 85 MHz strobe with 50% duty cycle; used as data valid signal for downstream logic. |
| PWR DOWN | Active-low power-down control | Asserting low forces all RxOUT pins to logic LOW and reduces supply current to ≤400 µA. |
| VCC (4 pins) | +3.3 V supply for TTL output drivers | Must be decoupled with 0.001 µF / 0.01 µF / 0.1 µF capacitors per NS AN recommendations. |
| LVDS VCC / LVDS GND | LVDS input bias supply | Separate power domain for LVDS receiver front-end; improves noise isolation from digital outputs. |
| PLL VCC / PLL GND | PLL core supply | Dedicated supply for clock recovery circuitry; requires highest priority decoupling for jitter minimization. |
Key Features
| Feature | Design Value |
|---|---|
| Failsafe input biasing | Guarantees HIGH output state on RxOUT when LVDS inputs are floating or unterminated - prevents undefined logic states in open-cable conditions. |
| 290 ps skew margin at 85 MHz | Enables use of cost-effective flat ribbon or twisted-pair cables up to ~2 m length while maintaining timing integrity across all 28 bits. |
| 50% duty cycle RxCLK OUT | Provides symmetrical timing window for downstream latch capture, reducing setup/hold violations in synchronous logic interfaces. |
| ±1 V common-mode tolerance | Allows >2 V ground potential difference between transmitter and receiver boards - critical for modular display subsystems with separate power domains. |
| No external PLL components | Integrates fully self-contained PLL with <10 ms lock time - eliminates BOM cost and layout area for loop filter capacitors or resistors. |
Applications
| Industrial LCD Timing Controller Interface | Medical Imaging Display Link |
|---|---|
Use Scenario: Connecting an FPGA-based timing controller to a high-resolution industrial LCD panel via flexible flat cable. IC Role / Device Role / Timing Role: DS90CR288ASLC/NOPB recovers clock and deserializes 28-bit RGB+HSYNC/VSYNC data from DS90CR287 transmitter for direct panel driving. Use Value: Replaces 28-wire parallel TTL interface with 10-wire LVDS link, cutting EMI by >30 dB and enabling cable lengths up to 1.5 m without signal integrity loss. | Use Scenario: Transmitting real-time ultrasound image data from acquisition board to diagnostic display unit in portable medical equipment. IC Role / Device Role / Timing Role: DS90CR288ASLC/NOPB serves as the final deserialization stage, converting serialized LVDS video stream into parallel pixel data for frame buffer ingestion. Use Value: Achieves 2.38 Gbps throughput with <290 ps skew margin, ensuring zero pixel corruption across 1280×1024 @ 75 Hz imaging sessions. |
| Avionics Head-Up Display (HUD) Video Interface | Test Equipment High-Speed Pattern Generator |
Use Scenario: Interfacing a graphics processor module to a HUD projection engine in aircraft cockpit systems. IC Role / Device Role / Timing Role: DS90CR288ASLC/NOPB receives serialized video over shielded Twin-Coax cable and delivers deterministic 28-bit parallel output synchronized to regenerated RxCLK OUT. Use Value: Meets DO-160E radiated emissions requirements due to LVDS's inherent common-mode noise rejection and 345 mV typical output swing. | Use Scenario: Integrating into automated test equipment (ATE) to validate LVDS serializer performance under production test conditions. IC Role / Device Role / Timing Role: DS90CR288ASLC/NOPB acts as reference receiver during bit-error-rate (BER) testing of DS90CR287-based DUTs using known-good pattern sequences. Use Value: Provides traceable 28-bit parallel output with documented RSPos timing windows (e.g., RSPos0 = 0.49–1.19 ns), enabling precise jitter and skew margin validation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS deserializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90CR288AMTD | Same die, identical electrical specs, but packaged in standard TSSOP (no lead-free/nickel-palladium-gold finish). | No RoHS compliance; unsuitable for lead-free assembly lines requiring Pb-free solder reflow profiles. | Select DS90CR288AMTD only if legacy assembly process uses SnPb solder and leaded finish is acceptable. |
| SN65LVDS32 | Single-channel LVDS receiver (4-bit), no integrated PLL, no clock recovery - requires external clock source. | Limited to point-to-point links with separate clock distribution; cannot replace DS90CR288ASLC/NOPB in Channel Link systems without redesign. | Use SN65LVDS32 only for simple LVDS line receivers where clock is distributed separately and data width is ≤4 bits. |
Compared with DS90CR288AMTD, DS90CR288ASLC/NOPB offers RoHS-compliant lead-free termination and Pb-free solder compatibility, while SN65LVDS32 lacks clock recovery and channel aggregation - making it unsuitable as a drop-in replacement in 28-bit Channel Link architectures.
Availability
DS90CR288ASLC/NOPB is available at Aetrix Electronics and suitable for industrial LCD timing controller interfaces, medical imaging display links, avionics head-up display video interfaces, and test equipment high-speed pattern generators requiring stable component supply and long-term lifecycle support.
Supply support for DS90CR288ASLC/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments acquired National Semiconductor in 2011 and maintains full technical and manufacturing continuity for legacy Channel Link products.
The DS90CR288ASLC/NOPB belongs to TI's high-speed interface portfolio, designed specifically to replace wide parallel TTL buses in digital video, medical imaging, and industrial display systems with robust, low-EMI LVDS serial links.
FAQ
What is the function of the PWR DOWN pin on DS90CR288ASLC/NOPB?
The PWR DOWN pin on DS90CR288ASLC/NOPB is an active-low control input that places the receiver into low-power mode when asserted. In this state, all 28 RxOUT pins are driven LOW, and supply current drops to ≤400 µA. This feature enables dynamic power gating during idle periods in display subsystems without disrupting system-level reset sequencing. DS90CR288ASLC/NOPB resumes normal operation within 1 µs after PWR DOWN is deasserted, provided RxCLK IN± is stable.
Does DS90CR288ASLC/NOPB require external termination resistors?
Yes, DS90CR288ASLC/NOPB requires external 100 Ω differential termination resistors across each LVDS input pair (RxIN+ to RxIN−, and RxCLK IN+ to RxCLK IN−) at the receiver board. These resistors must be placed as close as possible to the DS90CR288ASLC/NOPB input pins to minimize stub length and ensure proper impedance matching to the cable's differential characteristic impedance (typically 90–120 Ω). No pull-up or pull-down resistors are needed - the DS90CR288ASLC/NOPB input stage is internally biased.
Can DS90CR288ASLC/NOPB operate with a 5 V supply?
No, DS90CR288ASLC/NOPB is strictly a +3.3 V device and is not 5 V tolerant. Its absolute maximum supply voltage is +4 V, and recommended operating range is 3.0–3.6 V. Applying 5 V to VCC, LVDS VCC, or PLL VCC will exceed absolute maximum ratings and may cause permanent damage. For 5 V systems, the legacy DS90CR284 (5 V Channel Link receiver) must be used instead - DS90CR288ASLC/NOPB is not backward-compatible with 5 V logic levels on any pin.
What is the significance of the 290 ps skew margin specification for DS90CR288ASLC/NOPB?
The 290 ps skew margin for DS90CR288ASLC/NOPB defines the maximum allowable timing misalignment between the earliest and latest arriving LVDS data bits across all four data lanes at 85 MHz operation. This margin accounts for cable skew, inter-symbol interference, and source clock jitter, ensuring reliable data sampling even with non-ideal cabling. It directly enables use of cost-effective flat ribbon or twisted-pair cables up to ~1.8 m in length without requiring precision-matched-length conductors - a key enabler for modular display subsystem design.
How does DS90CR288ASLC/NOPB handle floating or unterminated LVDS inputs?
DS90CR288ASLC/NOPB incorporates internal failsafe bias circuitry that pulls LVDS inputs to a defined HIGH state when floating or unterminated. As a result, all 28 RxOUT pins default to logic HIGH, and RxCLK OUT remains HIGH if the clock input is also floating. This behavior prevents metastability or undefined logic states during cable disconnect, power sequencing, or hot-swap events - a critical reliability feature in field-deployed display systems. The failsafe threshold is guaranteed across temperature and voltage ranges per National Semiconductor's original characterization.
DS90CR288ASLC/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-LFBGA
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 64-NFBGA (8x8)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
DS90CR288ASLC/NOPB FAQ
1.How can I place an order for DS90CR288ASLC/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90CR288ASLC/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90CR288ASLC/NOPB reliable?
The price and inventory of DS90CR288ASLC/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90CR288ASLC/NOPB is usually 5 days.
3.What payment methods are accepted for DS90CR288ASLC/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90CR288ASLC/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90CR288ASLC/NOPB?
DS90CR288ASLC/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90CR288ASLC/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90CR288ASLC/NOPB?
For technical support, including DS90CR288ASLC/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90CR288ASLC/NOPB requirements.
6.How does Aetrix verify that DS90CR288ASLC/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90CR288ASLC/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90CR288ASLC/NOPB meets industry standards.
7.What is the process for return or replacement of DS90CR288ASLC/NOPB?
All DS90CR288ASLC/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90CR288ASLC/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90CR288ASLC/NOPB part is unused and in its original packaging.
Return procedure for DS90CR288ASLC/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90CR288ASLC/NOPB Tags
-
NVT4857UKAZ
NXP Semiconductors
-
TCA8418RTWR
Texas Instruments
-
PCA9546APWR
Texas Instruments
-
MD0100N8-G
Microchip Technology
-
PCA9548APW,118
NXP Semiconductors
-
PCA9540BDP,118
NXP Semiconductors
-
PCA9548APWR
Texas Instruments
-
PCA9546APW,118
NXP Semiconductors
-
PTN3360DBS,518
NXP Semiconductors
-
PCA9546ABS,118
NXP Semiconductors
-
PCA9518PWR
Texas Instruments
-
PCA9545APW,118
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
