Texas Instruments DS90CR484AVJD/NOPB

Overview

DS90CR484AVJD/NOPB from Texas Instruments is a 48-bit LVDS deserializer IC that converts eight serialized LVDS data streams and one LVDS clock into parallel 48-bit CMOS/TTL output data. It operates at input clock frequencies from 33 MHz to 112 MHz, delivers up to 5.38 Gbits/sec bandwidth, supports cable deskew of ±1 LVDS bit time (up to 80 MHz), and features DC-balanced data recovery for reduced ISI in long-cable applications such as industrial displays and machine vision interfaces.

For engineers reviewing the DS90CR484AVJD/NOPB datasheet, DS90CR484AVJD/NOPB pinout, DS90CR484AVJD/NOPB application, or DS90CR484AVJD/NOPB equivalent, key selection criteria include supported clock range (33–112 MHz), deskew capability (±1 TBIT, DC-balance mode only), pre-emphasis compatibility, LVDS receiver input range (0–2.4 V), and 100-lead TQFP package thermal performance (2.3 W max power dissipation).

Technical Context

The DS90CR484AVJD/NOPB implements a PLL-based LVDS receiver with integrated deskew logic active only when BAL = HIGH on the companion DS90CR483A transmitter and DESKEW = HIGH on this device. It recovers 48-bit parallel data using a phase-aligned sampling strobe tuned in 0.3 TBIT steps across ±1 TBIT range, requiring DS_OPT low for ≥4 clock cycles to initiate calibration.

DC balancing is enforced end-to-end: the transmitter computes running word disparity and inverts data per cycle to minimize DC bias; the receiver expects and correctly interprets the embedded DCBAL bit. Pre-emphasis control is handled externally via the PRE pin on the transmitter - the receiver itself does not adjust drive strength but relies on clean eye opening enabled by proper pre-emphasis setting.

Key Specifications

Pinout & Package

DS90CR484AVJD/NOPB is housed in a 100-lead Thin Quad Flat Package (TQFP) with 0.5 mm pitch, exposed thermal pad, and flow-through pinout optimized for controlled-impedance routing and minimal signal crosstalk.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with DS90CR484MTD/NOPB, DS90CR484AVJD/NOPB offers identical functionality but lacks wettable flanks - critical for AOI in safety-critical production. Against SN65LVDS32, DS90CR484AVJD/NOPB adds full 48-bit deserialization, cable deskew, and DC-balance recovery - essential for long-distance, high-bandwidth video/data transport.

Availability

DS90CR484AVJD/NOPB is available at Aetrix Electronics and suitable for industrial display interface, machine vision camera link, medical imaging backplane, and avionics video distribution requiring stable component supply, long-cable signal integrity, and deterministic deskew calibration.

Supply support for DS90CR484AVJD/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions.

The DS90CR484AVJD/NOPB belongs to TI's Channel Link serializer/deserializer product line, engineered specifically to replace wide parallel TTL buses with compact, noise-immune LVDS links for display, imaging, and industrial data acquisition systems.

FAQ

What is the maximum cable length supported by DS90CR484AVJD/NOPB?

DS90CR484AVJD/NOPB supports cables exceeding 5 meters when used with its companion DS90CR483A transmitter, pre-emphasis enabled, and DC balance active. Performance depends on cable type, frequency, and pre-emphasis level - e.g., 5+ meters at 80 MHz with 1.2 V PRE, or 7 meters at 66 MHz with 1.5 V PRE, per TI Application Note SNLS291A.

Does DS90CR484AVJD/NOPB require external termination resistors?

Yes, DS90CR484AVJD/NOPB requires a 100 Ω differential termination resistor placed as close as possible to its RxIN[0:7]+/− and RxCLKIN+/− inputs. This matches standard twisted-pair cable impedance, suppresses reflections, and completes the LVDS current loop - omission causes signal integrity failure and deskew malfunction.

Can DS90CR484AVJD/NOPB operate without DC balance enabled on the transmitter?

Yes, DS90CR484AVJD/NOPB can receive non-DC-balanced data from DS90CR483A when BAL = LOW, but deskew functionality is disabled in this mode. RSKM margin drops significantly - e.g., 170 ps at 112 MHz - limiting usable cable length and increasing susceptibility to ISI in long runs.

How is deskew calibration initiated for DS90CR484AVJD/NOPB?

Deskew calibration for DS90CR484AVJD/NOPB begins when DESKEW is set HIGH and DS_OPT on the DS90CR483A transmitter is pulsed LOW for ≥4 clock cycles. During calibration, all RxOUT pins hold LOW while RxCLKOUT remains active; successful completion yields aligned sampling strobes across all eight LVDS lanes.

What thermal considerations apply to DS90CR484AVJD/NOPB in continuous operation?

DS90CR484AVJD/NOPB dissipates up to 2.3 W at full load and must be mounted with its exposed thermal pad soldered to a solid copper plane. Derating is 18.1 mW/°C above +25°C ambient; at +70°C, max allowable power drops to ~1.5 W. Thermal vias under the pad and airflow are recommended for sustained 112 MHz operation.