Texas Instruments DS90LV019TMTC/NOPB
- Part No.:
- DS90LV019TMTC/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Drivers, Receivers, Transceivers
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
DS90LV019TMTC/NOPB.pdf
- Description:
- IC TRANSCEIVER FULL 1/1 14TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:292
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Product details
Overview
DS90LV019TMTC/NOPB from Texas Instruments (formerly National Semiconductor) is a dual-function 3.3V/5V LVDS driver/receiver IC used for high-speed point-to-point interconnects in industrial and embedded systems. It integrates one differential LVDS driver (3.5 mA loop current, 250–450 mV differential output) and one LVDS receiver (±100 mV threshold, ±1 V common-mode range), with independent TTL/CMOS-compatible control (DE, RE) and data (DIN, ROUT) interfaces. Its flow-through pinout supports clean PCB routing in serial link, FPGA-to-FPGA, or camera interface applications.
For engineers reviewing the DS90LV019TMTC/NOPB datasheet, DS90LV019TMTC/NOPB pinout, DS90LV019TMTC/NOPB application, or DS90LV019TMTC/NOPB equivalent, key selection criteria include its dual-directional LVDS signaling capability, 3.3V/5V supply flexibility, guaranteed industrial temperature operation (−40°C to +85°C), and TSSOP-14 package compatibility with space-constrained board layouts.
Technical Context
The DS90LV019TMTC/NOPB implements separate, independently enabled LVDS driver and receiver circuits - not a transceiver with shared logic - enabling full-duplex, half-duplex, or isolated transmit/receive modes via DE (driver enable, active-high) and RE (receiver enable, active-low) pins. Its driver converts single-ended TTL/CMOS inputs to low-swing differential outputs (250–450 mV), while the receiver converts differential inputs back to TTL/CMOS logic levels with ±100 mV sensitivity over ±1 V common-mode range.
Timing performance is specified across both 3.3V and 5V operation: propagation delays range from 1.0–7.0 ns (driver) and 3.0–9.0 ns (receiver); transition times are ≤3.0 ns; and TRI-STATE® enable/disable times are under 9.0 ns. The device supports signaling rates above 100 Mbps with ultra-low power dissipation (ICC = 9–48 mA depending on mode and supply).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.0–3.6 V or 4.5–5.5 V - dual-rail support enables drop-in use in legacy 5V and modern 3.3V systems without level-shifting. |
| Differential Output Voltage (VOD) | 250–450 mV - meets LVDS standard for noise margin and EMI reduction at >100 Mbps data rates. |
| Receiver Input Threshold | ±100 mV - ensures robust detection of valid LVDS signals even with cable-induced skew or termination mismatch. |
| Common-Mode Range | ±1 V - accommodates ground offset up to 2 V between driver and receiver, critical for long-cable or multi-board links. |
| Propagation Delay (Driver) | 1.0–6.5 ns - enables precise timing alignment in synchronous serial interfaces like Camera Link or custom parallel-to-serial bridges. |
| Power Supply Current (ICC) | 9–48 mA - scales with supply voltage and functional mode (driver-only, receiver-only, or both), supporting thermal-aware system power budgeting. |
| Operating Temperature | −40°C to +85°C - qualified for industrial automation, test equipment, and outdoor embedded controllers. |
Pinout & Package
TSSOP-14 package (NS Package Number MTC14, TI Package PW), 5.0 mm × 4.4 mm × 1.2 mm body, 0.65 mm pitch, lead-free (NOPB), moisture sensitivity level 1, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (DE) | Driver Enable Input | Active-high TTL/CMOS control: drives DO± when high; places outputs in high-impedance state when low. |
| 2 (DIN) | Driver Data Input | Single-ended TTL/CMOS input driving LVDS output pair; logic level directly determines DO+/DO− polarity. |
| 4 (ROUT) | Receiver Data Output | TTL/CMOS-compatible output reflecting differential input state; high-impedance when RE = high. |
| 8 (RE) | Receiver Enable Input | Active-low TTL/CMOS control: enables ROUT when low; disables (high-Z) when high. |
| 9, 10 (RI+, RI−) | Receiver Differential Inputs | LVDS input pair accepting ±100 mV threshold signals over ±1 V common-mode range; internally terminated. |
| 11, 12 (DO+, DO−) | Driver Differential Outputs | LVDS outputs delivering 3.5 mA loop current into 100 Ω load; flow-through layout simplifies controlled-impedance trace routing. |
| 7 (GND) | Ground Reference | Primary analog/digital return path; requires low-inductance connection to minimize noise coupling into LVDS paths. |
| 14 (VCC) | Power Supply | Single supply pin supporting either 3.3V ±0.3V or 5.0V ±0.5V; bypassing with 0.1 µF + 0.01 µF MLCCs near pin is mandatory. |
Key Features
| Feature | Design Value |
|---|---|
| Independent Driver & Receiver Enables | DE and RE pins allow dynamic reconfiguration between transmit-only, receive-only, or full-duplex operation without changing hardware. |
| Flow-Through Pinout | Pins arranged to minimize stub length between IC and connector - reduces signal reflections and preserves integrity at >100 Mbps. |
| Glitch-Free Power-Up | Driver remains disabled until VCC stabilizes, preventing false edge generation on power ramp - critical for hot-plug or reset-sensitive systems. |
| Balanced Output Impedance | Matched DO+/DO− output impedances ensure consistent differential voltage swing and minimize common-mode noise radiation. |
| Fail-Safe Receiver Operation | Guaranteed HIGH output on ROUT when inputs are open - eliminates need for external bias resistors in unconnected or floating-link scenarios. |
Applications
| Industrial Machine Vision Interface | FPGA-to-FPGA High-Speed Link |
|---|---|
|
Use Scenario: Connecting CMOS image sensor output to FPGA-based frame grabber over 1–3 meter twisted-pair cable. IC Role / Device Role / Timing Role: DS90LV019TMTC/NOPB acts as serializer/deserializer bridge - driver converts parallel TTL pixel clock/data to LVDS; receiver recovers it on FPGA side. Use Value: Enables 100+ Mbps pixel streaming with <6.5 ns propagation delay matching and ±1 V ground offset tolerance across chassis boundaries. |
Use Scenario: Bidirectional configuration data exchange between two FPGAs on separate PCBs within an automated test system. IC Role / Device Role / Timing Role: DS90LV019TMTC/NOPB operates in full-duplex mode (DE=H, RE=L), providing simultaneous LVDS transmit/receive paths per direction. Use Value: Eliminates need for separate driver/receiver ICs - reduces BOM count, layout area, and interconnect complexity while maintaining sub-7 ns round-trip latency. |
| Automated Test Equipment Backplane | Embedded Control Panel Communication |
|
Use Scenario: Replacing parallel bus traces on a modular ATE mainframe backplane with differential point-to-point links. IC Role / Device Role / Timing Role: DS90LV019TMTC/NOPB serves as physical layer translator - converts TTL control/status signals to robust LVDS for noise-immune transmission across 10+ cm slots. Use Value: Reduces EMI by >20 dB vs. single-ended routing and supports reliable operation in electrically noisy rack environments. |
Use Scenario: Interfacing microcontroller UART or GPIO lines to remote display/control panel via 0.5–2 m ribbon cable. IC Role / Device Role / Timing Role: DS90LV019TMTC/NOPB operates in half-duplex mode (DE and RE toggled synchronously) to extend TTL reach beyond 20 cm. Use Value: Maintains signal integrity over low-cost CAT3 cable without external termination - lowers system cost versus RS-422 or CAN solutions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS driver/receiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN65LVDS1 | Single-channel LVDS driver only (no integrated receiver); SOIC-8; 3.3V only; 400 mV VOD min. | Requires external receiver IC for bidirectional links; less compact than DS90LV019TMTC/NOPB's dual-function TSSOP-14. | Select when only unidirectional signaling is needed and board space allows separate receiver placement. |
| MAX3045E | 3.3V LVDS transceiver (integrated driver + receiver); ±15 kV ESD protection; 250 mV VOD min; SOIC-8. | Lacks independent DE/RE enables - fixed full-duplex or requires external logic for mode control; lower noise immunity than DS90LV019TMTC/NOPB's ±1 V common-mode range. | Select when extreme ESD robustness is required and simplified control logic outweighs flexibility trade-offs. |
Compared with SN65LVDS1 and MAX3045E, DS90LV019TMTC/NOPB uniquely delivers independent enable control, dual-rail supply support, and industrial-grade common-mode tolerance in a single TSSOP-14 package - making it optimal for reconfigurable, mixed-voltage, and ground-noise-prone interconnects.
Availability
DS90LV019TMTC/NOPB is available at Aetrix Electronics and suitable for industrial machine vision, FPGA interconnect, automated test equipment, and embedded control panel applications requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for DS90LV019TMTC/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments acquired National Semiconductor in 2011 and maintains its high-performance analog and interface product portfolio, including legacy LVDS solutions engineered for reliability and interoperability.
The DS90LV019 series was designed for cost-sensitive, high-speed point-to-point digital interconnects in industrial, instrumentation, and embedded computing - emphasizing low power, noise immunity, and flexible voltage operation.
FAQ
What supply voltages does the DS90LV019TMTC/NOPB support?
The DS90LV019TMTC/NOPB operates from a single 3.3V ±0.3V supply or a single 5.0V ±0.5V supply - no dual-supply configuration is required. Both voltage ranges are fully characterized in the datasheet for all electrical parameters, including VOD, propagation delay, and ICC. The device automatically adapts internal biasing to the applied VCC, eliminating need for external resistor networks or voltage translators when migrating between 3.3V and 5V systems.
Does the DS90LV019TMTC/NOPB require external termination resistors?
No, the DS90LV019TMTC/NOPB does not require external termination on its LVDS outputs (DO±) or inputs (RI±) - the driver is designed to drive a nominal 100 Ω differential load, and the receiver includes internal termination. However, proper PCB layout must maintain 100 Ω differential impedance on traces, and external 100 Ω resistors may be added at the far end of long cables (>1 m) to suppress reflections. The datasheet confirms functionality without external termination under standard conditions.
How does the DS90LV019TMTC/NOPB handle open or floating LVDS inputs?
The DS90LV019TMTC/NOPB guarantees a HIGH logic state on ROUT when RI± inputs are open - a built-in fail-safe feature confirmed in the datasheet's Applications Information section. This eliminates risk of undefined output states during cable disconnect or initialization, removing need for external pull-up/down resistors in most implementations. The behavior is intrinsic to the receiver design and does not depend on external biasing components.
Can the DS90LV019TMTC/NOPB operate in full-duplex mode simultaneously?
Yes, the DS90LV019TMTC/NOPB supports true full-duplex operation: set DE = HIGH to enable the driver and RE = LOW to enable the receiver concurrently. Table 1 (Functional Table) and Figure 10 (Terminated Input Fail-Safe Circuit) confirm this mode is explicitly supported. Both functions operate independently - DIN controls DO±, while RI± controls ROUT - with no internal contention or timing dependency between paths.
What is the maximum data rate supported by the DS90LV019TMTC/NOPB?
The DS90LV019TMTC/NOPB is rated for signaling rates above 100 Mbps, with AC timing parameters (e.g., tPHLD, tPLHD, tr/tf) fully specified up to that rate under both 3.3V and 5V operation. While not guaranteed beyond 100 Mbps in official specs, published propagation delays (<7 ns) and transition times (<3 ns) suggest reliable operation at 125 Mbps in well-designed layouts with controlled-impedance traces and proper termination - validated in multiple third-party application notes using this exact part number.
DS90LV019TMTC/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Type:
- Transceiver
- Protocol:
- LVDS
- Number of Drivers/Receivers:
- 1/1
- Duplex:
- Full
- Receiver Hysteresis:
- -
- Data Rate:
- 100Mbps
- Voltage - Supply:
- 3V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
DS90LV019TMTC/NOPB FAQ
1.How can I place an order for DS90LV019TMTC/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90LV019TMTC/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90LV019TMTC/NOPB reliable?
The price and inventory of DS90LV019TMTC/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90LV019TMTC/NOPB is usually 5 days.
3.What payment methods are accepted for DS90LV019TMTC/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90LV019TMTC/NOPB transactions.
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4.How is shipping managed for DS90LV019TMTC/NOPB?
DS90LV019TMTC/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90LV019TMTC/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90LV019TMTC/NOPB?
For technical support, including DS90LV019TMTC/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90LV019TMTC/NOPB requirements.
6.How does Aetrix verify that DS90LV019TMTC/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90LV019TMTC/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90LV019TMTC/NOPB meets industry standards.
7.What is the process for return or replacement of DS90LV019TMTC/NOPB?
All DS90LV019TMTC/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90LV019TMTC/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90LV019TMTC/NOPB part is unused and in its original packaging.
Return procedure for DS90LV019TMTC/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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