Texas Instruments DS90LV027ATMX/NOPB
- Part No.:
- DS90LV027ATMX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Drivers, Receivers, Transceivers
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS90LV027ATMX/NOPB.pdf
- Description:
- IC TRANSCEIVER 2/0 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:6,124
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Product details
Overview
DS90LV027ATMX/NOPB from Texas Instruments is a dual LVDS differential driver IC designed for high-speed point-to-point data transmission. It delivers 360-mV differential output swing at 3.3-V supply, supports up to 350 MHz operation (700 Mbps), and features 0.7-ns max differential skew and 1.5-ns max propagation delay. It serves as an LVCMOS-to-LVDS translator in industrial automation and multi-function printer interfaces.
For engineers reviewing the DS90LV027ATMX/NOPB datasheet, DS90LV027ATMX/NOPB pinout, DS90LV027ATMX/NOPB application, or DS90LV027ATMX/NOPB equivalent, key selection criteria include differential skew tolerance, 3.3-V single-supply compatibility, SOIC-8 flow-through layout, and interoperability with TIA/EIA-644-compliant receivers such as DS90LV028A.
Technical Context
The DS90LV027ATMX/NOPB implements a current-mode LVDS driver architecture with two independent channels, each sourcing ±3.1 mA nominal loop current into a 100-Ω termination. Its balanced current-source design ensures flat power dissipation versus frequency-46 mW static, scalable with switching activity-and eliminates rail-to-rail overlap current typical of voltage-mode drivers.
It operates across −40°C to +85°C with 3.0–3.6 V supply, provides power-off protection (outputs enter high-impedance state when VCC = 0 V), and maintains <0.4 ns channel-to-channel skew. The device requires external 100-Ω differential termination and is incompatible with AC-coupled or unterminated configurations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 3.3 V ±0.3 V - Enables direct integration with 3.3-V logic systems without level-shifting. |
| Differential Output Swing | 360 mV typ. - Generates sufficient signal margin (>250 mV min.) for reliable detection by TIA/EIA-644 receivers. |
| Max Data Rate | 700 Mbps (350 MHz) - Supports high-bandwidth digital video, parallel bus serialization, and real-time control links. |
| Propagation Delay | 1.5 ns max. - Ensures tight timing alignment in synchronous multi-channel systems. |
| Differential Skew | 0.7 ns max. - Maintains inter-pair timing integrity critical for parallel LVDS buses and clock distribution. |
| Power Dissipation | 46 mW static - Reduces thermal load and simplifies thermal management in dense PCB layouts. |
| Operating Temperature | −40°C to +85°C - Certified for industrial environments including factory automation and grid infrastructure. |
Pinout & Package
DS90LV027ATMX/NOPB is housed in an 8-pin SOIC (D package), 4.90 mm × 3.91 mm body size, with gull-wing leads and RoHS-compliant matte tin (SN) finish. The flow-through pinout minimizes trace crossing and enables matched-length routing of differential pairs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (Pin 1) | Power supply input | 3.3-V primary supply; requires local 0.1-μF ceramic decoupling adjacent to pin. |
| DI 1 (Pin 2) | Input 1 | TTL/CMOS-compatible single-ended data input driving Channel 1. |
| DI 2 (Pin 3) | Input 2 | TTL/CMOS-compatible single-ended data input driving Channel 2. |
| GND (Pin 4) | Ground reference | Common return path for supply and signal currents; must connect to low-impedance ground plane. |
| DO− 2 (Pin 5) | Output 2, inverting | LVDS complementary output for Channel 2; routed with DO+ 2 as controlled-impedance differential pair. |
| DO+ 2 (Pin 6) | Output 2, non-inverting | LVDS true output for Channel 2; forms 100-Ω terminated differential pair with DO− 2. |
| DO+ 1 (Pin 7) | Output 1, non-inverting | LVDS true output for Channel 1; forms 100-Ω terminated differential pair with DO− 1. |
| DO− 1 (Pin 8) | Output 1, inverting | LVDS complementary output for Channel 1; routed with DO+ 1 as controlled-impedance differential pair. |
Key Features
| Feature | Design Value |
|---|---|
| Current-mode LVDS architecture | Delivers stable 3.1-mA loop current independent of frequency-enables predictable power scaling and low EMI. |
| Flow-through pinout | Separates inputs (Pins 2–3) and outputs (Pins 5–8) on opposite sides-simplifies layer stacking and differential trace length matching. |
| Power-off protection | Outputs automatically enter high-impedance state when VCC = 0 V-prevents back-driving or bus contention during hot-swap or power sequencing. |
| TIA/EIA-644 compliance | Fully conforms to LVDS electrical standards-guarantees interoperability with industry-standard receivers including DS90LV028A, SN65LVDS1, and MAX9100. |
| Industrial temperature range | Rated for −40°C to +85°C operation-validated for deployment in building automation controllers and outdoor grid monitoring equipment. |
Applications
| Multi-Function Printers | Factory Automation I/O Modules |
|---|---|
Use Scenario: High-speed transfer of raster image data between ASIC and print engine head. IC Role / Device Role / Timing Role: LVCMOS-to-LVDS serializer translating parallel pixel data into noise-immune differential streams. Use Value: 350-MHz capability supports >600-dpi printing at 30 ppm; 0.7-ns skew preserves pixel timing alignment across dual-channel scan lines. | Use Scenario: Isolating PLC CPU digital outputs from distributed I/O terminals over 2-meter ribbon cable. IC Role / Device Role / Timing Role: Robust differential driver enabling noise-tolerant communication in electrically noisy factory floors. Use Value: 360-mV swing and common-mode noise rejection ensure reliable operation despite 100-mV EMI coupling; SOIC-8 footprint fits space-constrained DIN-rail modules. |
| Grid Infrastructure Monitoring | Embedded Vision Systems |
Use Scenario: Transmitting synchronized sensor telemetry (voltage, current, phase) from substation RTUs to central SCADA. IC Role / Device Role / Timing Role: Low-skew LVDS transmitter maintaining timestamp coherence across dual analog-to-digital converter channels. Use Value: 0.4-ns channel-to-channel skew enables sub-microsecond time-of-arrival correlation; −40°C to +85°C rating supports outdoor cabinet deployment. | Use Scenario: Interfacing FPGA-based image preprocessor with CMOS image sensor requiring serialized clock/data lanes. IC Role / Device Role / Timing Role: Dual-channel LVDS driver generating synchronized pixel clock and data strobe signals. Use Value: 1.5-ns max propagation delay ensures <2-ns total jitter accumulation in 1080p60 pipelines; 46-mW dissipation avoids thermal derating in sealed enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN65LVDS1DR | Single-channel, 3.3-V LVDS driver; 400 Mbps max; SOIC-8 package; no power-off high-Z mode. | Suitable only for single-link applications; lacks dual-channel integration and fail-safe power-down behavior. | Select when board space permits discrete channel implementation and power sequencing excludes hot-swap scenarios. |
| MAX9100ESA+ | Single-channel, 5-V tolerant LVDS driver; 600 Mbps max; SOIC-8; higher ICC (25 mA typ.) and larger 500-mV swing. | Requires level translation for 3.3-V systems; higher power and EMI limit use in thermally constrained designs. | Choose only if legacy 5-V supply rails exist and system-level noise immunity justifies increased power and swing. |
Compared with SN65LVDS1DR and MAX9100ESA+, DS90LV027ATMX/NOPB uniquely combines dual-channel integration, 3.3-V native operation, power-off high-Z, and sub-nanosecond skew-making it optimal for compact, thermally sensitive, and hot-pluggable industrial interfaces where channel pairing and supply simplicity are critical.
Availability
DS90LV027ATMX/NOPB is available at Aetrix Electronics and suitable for industrial automation, grid infrastructure monitoring, and embedded vision systems requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.
Supply support for DS90LV027ATMX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies, with decades of leadership in interface ICs and industrial-grade signal conditioning.
The DS90LV027ATMX/NOPB belongs to TI's LVDS interface product line, engineered specifically for robust, low-power, high-speed differential signaling in noise-prone industrial and infrastructure applications.
FAQ
What is the maximum operating frequency supported by DS90LV027ATMX/NOPB?
The DS90LV027ATMX/NOPB supports a maximum operating frequency of 350 MHz, corresponding to a data rate of 700 Mbps under specified conditions (RL = 100 Ω, CL = 15 pF). This value is validated per the switching characteristics table in the official datasheet and reflects guaranteed performance across the full industrial temperature range.
Does DS90LV027ATMX/NOPB require external termination resistors?
Yes, DS90LV027ATMX/NOPB requires a 100-Ω differential termination resistor placed at the receiver end of the transmission line. As a current-mode LVDS driver, it relies on this resistive load to convert output current into a detectable differential voltage (VOD); operation without termination violates TIA/EIA-644 compliance and risks signal integrity failure.
Can DS90LV027ATMX/NOPB interface directly with 5-V logic inputs?
No, DS90LV027ATMX/NOPB accepts TTL/CMOS inputs referenced to its 3.3-V supply (VIH = 2 V min., VIL = 0.8 V max.) and is not 5-V tolerant. Direct connection to 5-V logic sources may exceed absolute maximum input voltage ratings (−0.3 V to 3.6 V) and cause permanent damage. Level-shifting circuitry is required for 5-V system interfacing.
What happens to DS90LV027ATMX/NOPB outputs when VCC is removed?
When VCC is removed or driven to 0 V, DS90LV027ATMX/NOPB outputs enter a high-impedance state due to built-in power-off protection. This prevents back-driving of the LVDS bus and eliminates contention in hot-swap or partial-power-down scenarios-ensuring safe operation in modular industrial systems.
Is DS90LV027ATMX/NOPB compatible with the DS90LV028A receiver?
Yes, DS90LV027ATMX/NOPB is explicitly designed to pair with the DS90LV028A dual LVDS receiver. Both devices share matched electrical specifications-including 360-mV differential swing, 100-Ω termination requirement, and TIA/EIA-644 compliance-enabling seamless point-to-point link implementation with minimal design validation effort.
DS90LV027ATMX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Driver
- Protocol:
- LVDS
- Number of Drivers/Receivers:
- 2/0
- Duplex:
- -
- Receiver Hysteresis:
- -
- Data Rate:
- 600Mbps
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
DS90LV027ATMX/NOPB FAQ
1.How can I place an order for DS90LV027ATMX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90LV027ATMX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90LV027ATMX/NOPB reliable?
The price and inventory of DS90LV027ATMX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90LV027ATMX/NOPB is usually 5 days.
3.What payment methods are accepted for DS90LV027ATMX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90LV027ATMX/NOPB transactions.
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4.How is shipping managed for DS90LV027ATMX/NOPB?
DS90LV027ATMX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90LV027ATMX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90LV027ATMX/NOPB?
For technical support, including DS90LV027ATMX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90LV027ATMX/NOPB requirements.
6.How does Aetrix verify that DS90LV027ATMX/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90LV027ATMX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90LV027ATMX/NOPB meets industry standards.
7.What is the process for return or replacement of DS90LV027ATMX/NOPB?
All DS90LV027ATMX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90LV027ATMX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90LV027ATMX/NOPB part is unused and in its original packaging.
Return procedure for DS90LV027ATMX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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