Texas Instruments DS90LV032ATMX/NOPB
- Part No.:
- DS90LV032ATMX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Drivers, Receivers, Transceivers
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS90LV032ATMX/NOPB.pdf
- Description:
- IC TRANSCEIVER 0/4 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:6,583
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Product details
Overview
DS90LV032ATMX/NOPB from Texas Instruments is a quad 3.3-V LVDS differential line receiver with 400 Mbps data rate support, 3.3-ns max propagation delay, and fail-safe operation for open/short/terminated inputs. It translates low-voltage (350 mV typical) differential signals to 3-V CMOS logic levels and supports TRI-STATE outputs for bus multiplexing in high-speed industrial serial links.
For engineers reviewing the DS90LV032ATMX/NOPB datasheet, DS90LV032ATMX/NOPB pinout, DS90LV032ATMX/NOPB application, or DS90LV032ATMX/NOPB equivalent, key selection criteria include differential skew (0.1 ns typ), channel-to-channel skew (0.1 ns typ), fail-safe output behavior, 3.3-V supply compatibility, and SOIC/TSSOP package options for PCB layout flexibility.
Technical Context
The DS90LV032ATMX/NOPB implements four independent LVDS receivers with internal fail-safe biasing that forces HIGH output under open, shorted, or 100-Ω-terminated input conditions. Each channel features matched differential input thresholds (±20 mV min) and operates across a 0.1–2.3 V common-mode range centered at 1.2 V.
It supports dual enable control (EN active-high and EN* active-low OR-ed), delivers 2.7–3.0 V CMOS outputs at –0.4 mA sink/source, and achieves 200 MHz maximum operating frequency with <1.2 ns rise/fall times. Power-down mode reduces supply current to 3–5 mA while maintaining high-impedance inputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | 400 Mbps (200 MHz) - enables high-speed point-to-point serial links in factory automation and grid infrastructure |
| Propagation Delay | 1.8–3.3 ns - ensures tight timing alignment in multi-channel synchronous interfaces |
| Differential Skew | 0.1 ns typical - minimizes intra-channel timing mismatch critical for clean eye diagrams |
| Channel Skew | 0.1 ns typical - maintains inter-channel synchronization for parallel data recovery |
| Supply Voltage | 3.0–3.6 V - compatible with standard 3.3-V systems and interoperable with legacy 5-V LVDS networks |
| Input Sensitivity | 350 mV typical VID - allows robust reception over noisy industrial cabling with low-power drivers |
| Fail-Safe Output | HIGH for open/short/100-Ω terminated inputs - prevents undefined logic states during cable disconnect or driver power loss |
Pinout & Package
DS90LV032ATMX/NOPB is available in 16-pin TSSOP (5.00 mm × 4.40 mm) and SOIC (9.90 mm × 3.91 mm) packages. Both share identical pinout and thermal characteristics per TI SNLS011D Rev D.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (Pin 16) | Power supply | 3.3-V ±0.3-V supply input; requires local 0.1-µF + 0.01-µF decoupling |
| GND (Pin 8) | Ground reference | Common return path for all receiver channels and enable logic |
| EN (Pin 4) | Enable control | Active-high input; OR-ed with EN* to disable all outputs into high-impedance state |
| EN* (Pin 12) | Enable control | Active-low input; OR-ed with EN for flexible system-level enable signaling |
| RIN1+ to RIN4+ (Pins 2,6,10,14) | Differential input | Non-inverting inputs for Channels 1–4; accept 0.1–2.3 V common-mode signals |
| RIN1− to RIN4− (Pins 1,7,9,15) | Differential input | Inverting inputs for Channels 1–4; support fail-safe biasing when left floating |
| ROUT1 to ROUT4 (Pins 3,5,11,13) | CMOS output | 3-V logic-level outputs; drive TTL/CMOS loads with 2.7 V min VOH and 0.25 V max VOL |
Key Features
| Feature | Design Value |
|---|---|
| Fail-safe input handling | Guarantees HIGH output for open, shorted, or 100-Ω-terminated inputs-eliminates need for external bias resistors in most industrial deployments |
| Low-power operation | 40 mW static dissipation at 3.3 V-reduces thermal load in dense PCB layouts and enables fanless industrial enclosures |
| Interoperability | Compatible with ANSI/TIA/EIA-644 LVDS standard and functional with 5-V LVDS drivers-simplifies migration from legacy systems |
| TRI-STATE output control | Independent EN/EN* enables bus sharing across multiple receivers without external logic-reduces component count in multi-drop configurations |
| ESD robustness | ±4.5 kV HBM rating-meets industrial IEC 61000-4-2 Level 3 requirements without additional protection circuitry |
Applications
| Factory Automation I/O Link | Smart Grid Sensor Interface |
|---|---|
Use Scenario: High-speed serial transmission of analog sensor readings and digital actuator commands across noisy plant-floor cabling. IC Role / Device Role / Timing Role: LVDS receiver converting differential signals from remote I/O modules into clean 3-V CMOS logic for PLC backplane processing. Use Value: 0.1-ns channel skew preserves timing integrity across 4-channel synchronized sampling; fail-safe output prevents spurious commands during cable disconnection. | Use Scenario: Reliable communication between substation RTUs and distributed fault detectors over twisted-pair wiring. IC Role / Device Role / Timing Role: Quad receiver conditioning LVDS data streams from multiple sensors before feeding FPGA-based protocol engines. Use Value: 350-mV input sensitivity enables long-distance (>10 m) transmission using CAT5 cable; industrial temperature range (–40°C to 85°C) ensures outdoor deployment reliability. |
| Industrial Camera Interface | Motor Drive Feedback Loop |
Use Scenario: Receiving pixel clock and image data from high-resolution area-scan cameras in machine vision systems. IC Role / Device Role / Timing Role: LVDS receiver recovering serialized video data at 200 MHz with minimal jitter accumulation across four differential pairs. Use Value: 3.3-ns max propagation delay and 1.2-ns max transition time maintain tight setup/hold margins for FPGA capture logic. | Use Scenario: Capturing encoder quadrature signals and current-sense feedback from servo drives in real-time motion control loops. IC Role / Device Role / Timing Role: Differential receiver translating noise-immune LVDS encoder outputs into deterministic CMOS timing signals for microcontroller input capture units. Use Value: Common-mode range (0.1–2.3 V) accommodates ground potential shifts between motor and controller; fail-safe ensures safe default state during encoder cable faults. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS receiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX9107ESE+ | Single-channel LVDS receiver; 250 Mbps max data rate; 5-V tolerant inputs; no integrated fail-safe | Requires external biasing for fail-safe; suited for lower-speed, mixed-voltage designs where space constraints favor single-channel devices | Select when only one channel is needed and 5-V interface compatibility outweighs quad integration and fail-safe convenience |
| SN65LVDS32DR | Quad LVDS receiver; 400 Mbps rated; 3.3-V supply; no EN/EN* dual-enable; failsafe only for open inputs | Lacks dual-enable control and short-circuit/termination fail-safe; requires external termination bias for robust fault coverage | Choose for cost-sensitive volume production where simplified enable logic and reduced feature set are acceptable trade-offs |
Compared with MAX9107ESE+ and SN65LVDS32DR, DS90LV032ATMX/NOPB provides full quad integration with dual-enable control, comprehensive fail-safe (open/short/terminated), and guaranteed 400 Mbps performance-making it optimal for space-constrained, fault-tolerant industrial serial links requiring zero external bias components.
Availability
DS90LV032ATMX/NOPB is available at Aetrix Electronics and suitable for factory automation I/O links, smart grid sensor interfaces, and industrial camera data acquisition requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for DS90LV032ATMX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions for industrial, automotive, and communications markets.
The DS90LV032ATMX/NOPB belongs to TI's LVDS interface product line, engineered specifically for high-speed, low-power, noise-immune serial communication in harsh industrial environments.
FAQ
What is the maximum operating frequency supported by DS90LV032ATMX/NOPB?
The DS90LV032ATMX/NOPB supports a maximum operating frequency of 200 MHz (400 Mbps), verified under recommended conditions (VCC = 3.3 V, TA = 25°C, CL = 10 pF). This specification holds across the full industrial temperature range (–40°C to 85°C) and applies to all four channels simultaneously, as confirmed in TI SNLS011D Section 6.6.
Does DS90LV032ATMX/NOPB require external termination resistors?
Yes, DS90LV032ATMX/NOPB requires a 100-Ω differential termination resistor placed as close as possible to its RIN+/RIN– input pins. The device itself does not integrate termination; this external resistor matches the characteristic impedance of the transmission medium (e.g., twisted-pair cable or PCB traces) and is essential for signal integrity and proper LVDS operation per ANSI/TIA/EIA-644 compliance.
How does the fail-safe function behave on DS90LV032ATMX/NOPB during input faults?
DS90LV032ATMX/NOPB guarantees a HIGH output state for all four channels under three fault conditions: open inputs (unused channels left floating), shorted inputs (RIN+ tied to RIN−), and 100-Ω-terminated inputs (driver disconnected). This behavior is implemented via internal biasing and requires no external components, ensuring deterministic logic states during cable faults or driver power loss.
Can DS90LV032ATMX/NOPB interface directly with 5-V LVDS drivers?
Yes, DS90LV032ATMX/NOPB is interoperable with existing 5-V LVDS networks per its datasheet. Its input voltage tolerance (–0.3 V to 3.9 V) and common-mode range (0.1–2.3 V) accommodate the 1.2-V common-mode offset typical of 5-V LVDS drivers, enabling seamless integration without level-shifting circuitry in mixed-voltage systems.
What is the power consumption of DS90LV032ATMX/NOPB in enabled versus disabled mode?
In enabled mode, DS90LV032ATMX/NOPB draws 10–15 mA supply current (ICC) at 3.3 V, equating to ~40 mW static power. In disabled mode (EN = GND, EN* = VCC), supply current drops to 3–5 mA (ICCZ), reducing power to ~12 mW. This low-power shutdown capability supports energy-efficient system design and thermal management in dense industrial PCB layouts.
DS90LV032ATMX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Receiver
- Protocol:
- LVDS
- Number of Drivers/Receivers:
- 0/4
- Duplex:
- -
- Receiver Hysteresis:
- -
- Data Rate:
- 400Mbps
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
DS90LV032ATMX/NOPB FAQ
1.How can I place an order for DS90LV032ATMX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90LV032ATMX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90LV032ATMX/NOPB reliable?
The price and inventory of DS90LV032ATMX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90LV032ATMX/NOPB is usually 5 days.
3.What payment methods are accepted for DS90LV032ATMX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90LV032ATMX/NOPB transactions.
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4.How is shipping managed for DS90LV032ATMX/NOPB?
DS90LV032ATMX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90LV032ATMX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90LV032ATMX/NOPB?
For technical support, including DS90LV032ATMX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90LV032ATMX/NOPB requirements.
6.How does Aetrix verify that DS90LV032ATMX/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90LV032ATMX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90LV032ATMX/NOPB meets industry standards.
7.What is the process for return or replacement of DS90LV032ATMX/NOPB?
All DS90LV032ATMX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90LV032ATMX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90LV032ATMX/NOPB part is unused and in its original packaging.
Return procedure for DS90LV032ATMX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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