Texas Instruments DS90LV047ATMX/NOPB
- Part No.:
- DS90LV047ATMX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Drivers, Receivers, Transceivers
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
DS90LV047ATMX/NOPB.pdf
- Description:
- IC TRANSCEIVER 4/0 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:9,140
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Product details
Overview
DS90LV047ATMX/NOPB from Texas Instruments is a quad CMOS LVDS differential line driver operating at 3.3 V, delivering >400-Mbps data rates (200 MHz), 300-ps typical differential skew, and 1.7-ns max propagation delay. It translates TTL/CMOS inputs to ±350-mV LVDS outputs and supports TRI-STATE control via EN/EN* for ultra-low idle power (13 mW). Used in high-speed point-to-point interfaces such as multifunction printers and LVDS–LVCMOS translation.
For engineers reviewing the DS90LV047ATMX/NOPB datasheet, DS90LV047ATMX/NOPB pinout, DS90LV047ATMX/NOPB application, or DS90LV047ATMX/NOPB equivalent, key selection criteria include differential skew tolerance, flow-through PCB layout compatibility, LVDS standard compliance (TIA/EIA-644), and industrial temperature range (−40°C to +85°C) support.
Technical Context
The DS90LV047ATMX/NOPB implements a current-mode LVDS driver architecture with fixed 3.1-mA output loop current, requiring external 100-Ω termination to generate 310-mV typical differential voltage (VOD). Its AND-gated EN/EN* control enables simultaneous TRI-STATE of all four channels, achieving high-impedance outputs during power-down.
It operates strictly within 3.0–3.6 V supply range and demands matched differential trace routing due to its 0.4-ns max channel-to-channel skew and 1.2-ns max part-to-part skew. The device is not AC-coupled or unterminated-capable-resistive termination is mandatory for functional operation per its current-source design.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | 200 MHz max (400 Mbps); defines maximum usable clock frequency for reliable NRZ signaling |
| Differential Skew | 0.4 ns max (channel-to-channel); limits timing misalignment between parallel LVDS lanes |
| Propagation Delay | 1.7 ns max; determines worst-case signal path latency in high-speed interconnects |
| Supply Voltage | 3.3 V ±0.3 V; requires tight regulation and local decoupling (0.1 µF + 0.001 µF) |
| Output Differential Voltage | 250–450 mV (at 100 Ω load); sets receiver noise margin and compatibility with TIA/EIA-644 |
| Idle Power Dissipation | 13 mW typical (TRI-STATE active); enables low-power standby in burst-mode systems |
| Operating Temperature | −40°C to +85°C; validated for industrial-grade embedded and peripheral applications |
Pinout & Package
DS90LV047ATMX/NOPB is packaged in a 16-pin TSSOP (PW package), 5.00 mm × 4.40 mm body size, with exposed pad not present. Pin numbering follows standard top-view SOIC/TSSOP convention.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (EN) | Enable input | Active-high enable; must be high AND EN* low/open to activate all drivers |
| 2,3,6,7 (DIN1–DIN4) | Input | TTL/CMOS-compatible logic inputs; accept 0–3.3 V swing |
| 4 (VCC) | Power supply | +3.3 V supply pin; requires local high-frequency decoupling |
| 5 (GND) | Ground | Reference return for all signals and supply; critical for LVDS common-mode stability |
| 8 (EN*) | Inverted enable input | Active-low enable; ANDed with EN; open or low enables, high disables |
| 9,12,13,16 (DOUT−1–DOUT−4) | Inverting output | LVDS complementary output; paired with DOUT+ for differential signaling |
| 10,11,14,15 (DOUT+1–DOUT+4) | Non-inverting output | LVDS primary output; forms 100-Ω terminated differential pair with DOUT− |
Key Features
| Feature | Design Value |
|---|---|
| Flow-through pinout | Enables straight-through PCB routing-inputs on left, outputs on right-minimizing trace length mismatch and crosstalk |
| TRI-STATE enable logic | AND-gated EN/EN* allows fail-safe disable: both pins open → outputs disabled, preventing bus contention |
| Current-mode LVDS output | 3.1-mA constant-current source ensures stable VOD across process/voltage/temperature, eliminating supply-dependent swing variation |
| Interoperability with 5-V receivers | ±350-mV differential swing and 1.2-V common-mode level meet TIA/EIA-644, enabling direct interface to legacy 5-V LVDS receivers |
| Industrial temperature rating | Validated operation from −40°C to +85°C confirms suitability for printer engines, industrial controllers, and factory-floor peripherals |
Applications
| High-Speed Printer Data Link | LVDS–LVCMOS Level Translation |
|---|---|
Use Scenario: Transmitting raster image data between controller ASIC and print engine head over 10–30 cm PCB traces. IC Role / Device Role / Timing Role: Quad LVDS driver converting parallel LVCMOS pixel data into four differential pairs for EMI-resistant transmission. Use Value: 200 MHz data rate supports >1200 dpi printing at 30 ppm; 0.4 ns skew preserves pixel alignment across parallel lanes. | Use Scenario: Bridging a 3.3-V FPGA I/O bank to a legacy 5-V LVDS display interface. IC Role / Device Role / Timing Role: Signal translator maintaining timing integrity while adapting voltage domain and noise immunity. Use Value: ±350-mV differential output and 1.2-V common-mode comply with TIA/EIA-644, ensuring interoperability without level-shifting circuitry. |
| Industrial Camera Interface | Embedded Display Interconnect |
Use Scenario: Sending uncompressed video frames from CMOS image sensor to host processor over flex cable. IC Role / Device Role / Timing Role: High-fidelity differential transmitter preserving edge integrity and minimizing jitter-induced pixel errors. Use Value: 1.7 ns max propagation delay and 300 ps typical skew maintain sub-pixel timing accuracy over 15 cm CAT5 cable. | Use Scenario: Driving LVDS input of an LCD timing controller from a microcontroller with LVCMOS GPIOs. IC Role / Device Role / Timing Role: Low-power, pin-efficient interface IC enabling compact display module integration. Use Value: 13 mW idle power in TRI-STATE mode reduces system standby consumption; TSSOP package fits space-constrained display bezels. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN65LVDS047DR | Same 16-pin TSSOP package, identical pinout, and matching electrical specs (200 MHz, 3.3 V, TIA/EIA-644 compliant); TI second-source variant | No functional deviation; drop-in replacement verified in TI reference designs | Select when dual-sourcing or extended lifecycle assurance is required |
| MAX9107ESE+ | Quad LVDS driver in 16-pin SOIC; 250 Mbps max (vs. 400 Mbps), higher ICC (15 mA vs. 8 mA), no EN*/EN AND logic-single enable only | Limited to lower-speed industrial sensors or legacy displays where skew <0.6 ns suffices | Choose only if SOIC footprint is mandated and 200 MHz margin is acceptable |
Compared with DS90LV047ATMX/NOPB, SN65LVDS047DR offers identical performance and pin compatibility for supply chain resilience, while MAX9107ESE+ trades speed and enable flexibility for SOIC availability-making DS90LV047ATMX/NOPB optimal for new designs demanding 400 Mbps and robust TRI-STATE control.
Availability
DS90LV047ATMX/NOPB is available at Aetrix Electronics and suitable for high-speed printer interfaces, industrial camera links, LVDS–LVCMOS translation, and embedded display interconnects requiring stable component supply across multi-year production cycles.
Supply support for DS90LV047ATMX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies, with leadership in interface, power management, and signal chain solutions.
The DS90LV047ATMX/NOPB belongs to TI's LVDS interface product line, engineered for ultra-low-power, high-speed point-to-point digital interconnects in industrial, imaging, and peripheral applications.
FAQ
What is the minimum recommended termination resistance for DS90LV047ATMX/NOPB?
The DS90LV047ATMX/NOPB requires a resistive termination between 90 Ω and 130 Ω, with 100 Ω being the nominal value specified in the datasheet. This resistor must be placed at the receiver end of the differential pair to convert the 3.1-mA current output into the required 310-mV typical differential voltage (VOD). Operation without termination is not functional-the device is a current-mode driver and cannot drive unterminated or AC-coupled lines.
Does DS90LV047ATMX/NOPB support hot-plug or live insertion?
No, DS90LV047ATMX/NOPB does not support hot-plug operation. Its absolute maximum ratings specify that input voltages must remain within −0.3 V to VCC + 0.3 V, and the device lacks built-in I/O protection for insertion under bias. Applying signals before VCC ramp-up-or removing VCC while inputs are driven-may exceed ESD or latch-up limits. System-level hot-swap capability requires external protection circuitry beyond DS90LV047ATMX/NOPB's native functionality.
Can DS90LV047ATMX/NOPB drive multiple receivers in a multidrop configuration?
DS90LV047ATMX/NOPB is designed for point-to-point use per TIA/EIA-644. While multidrop is electrically possible with careful impedance control, it is not characterized or guaranteed. Adding receivers increases capacitive loading and alters termination, degrading VOD, increasing skew, and raising jitter-especially beyond 2 receivers. TI recommends using a dedicated LVDS repeater or fanout buffer (e.g., DS90LV049) instead of relying on DS90LV047ATMX/NOPB for multidrop.
What is the purpose of the EN* pin on DS90LV047ATMX/NOPB, and how should it be handled if unused?
The EN* pin on DS90LV047ATMX/NOPB is an active-low enable that is ANDed with EN to control TRI-STATE. If unused, EN* must be tied to GND (not left floating) to ensure predictable enable behavior. Leaving EN* open may result in indeterminate output states due to noise coupling or internal leakage; TI explicitly states that "if both EN and EN* are open circuit, then the driver is disabled"-but this is not a robust default. For reliable operation, connect EN* to GND unless active inversion is required.
Is DS90LV047ATMX/NOPB compatible with 5-V LVDS receivers, and what ensures interoperability?
Yes, DS90LV047ATMX/NOPB is interoperable with 5-V LVDS receivers. Interoperability is ensured by strict adherence to the TIA/EIA-644 LVDS standard: its ±350-mV differential output swing and 1.2-V common-mode voltage (VOS) fall within the receiver input acceptance window (typically ±100 mV to ±400 mV differential, 0–2.4 V common-mode). No level-shifting circuitry is needed-this compatibility is verified in TI's application notes and cross-tested with industry-standard 5-V LVDS receivers like DS90LV048A.
DS90LV047ATMX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Driver
- Protocol:
- LVDS
- Number of Drivers/Receivers:
- 4/0
- Duplex:
- -
- Receiver Hysteresis:
- -
- Data Rate:
- 400Mbps
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
DS90LV047ATMX/NOPB FAQ
1.How can I place an order for DS90LV047ATMX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90LV047ATMX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90LV047ATMX/NOPB reliable?
The price and inventory of DS90LV047ATMX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90LV047ATMX/NOPB is usually 5 days.
3.What payment methods are accepted for DS90LV047ATMX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90LV047ATMX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90LV047ATMX/NOPB?
DS90LV047ATMX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90LV047ATMX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90LV047ATMX/NOPB?
For technical support, including DS90LV047ATMX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90LV047ATMX/NOPB requirements.
6.How does Aetrix verify that DS90LV047ATMX/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90LV047ATMX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90LV047ATMX/NOPB meets industry standards.
7.What is the process for return or replacement of DS90LV047ATMX/NOPB?
All DS90LV047ATMX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90LV047ATMX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90LV047ATMX/NOPB part is unused and in its original packaging.
Return procedure for DS90LV047ATMX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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