My Inquiry
My Account
Texas Instruments DS90LV049TMTX/NOPB
- Part No.:
- DS90LV049TMTX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Drivers, Receivers, Transceivers
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
DS90LV049TMTX/NOPB.pdf
- Description:
- IC TRANSCEIVER FULL 2/2 16TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:15,453
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90LV049TMTX/NOPB from Texas Instruments is a 3.3 V dual LVDS line driver with integrated dual LVDS line receiver, supporting up to 400 Mbps data rates, 50 ps typical channel-to-channel skew, and flow-through pinout for simplified PCB routing in point-to-point high-speed interconnects used in industrial imaging and embedded video interfaces.
For engineers reviewing the DS90LV049TMTX/NOPB datasheet, DS90LV049TMTX/NOPB pinout, DS90LV049TMTX/NOPB application, or DS90LV049TMTX/NOPB equivalent, this page delivers verified electrical parameters, true pin functions, industrial temperature operation (−40°C to +85°C), TSSOP-16 package mapping, and two confirmed alternative parts with documented functional and layout trade-offs.
Technical Context
The DS90LV049TMTX/NOPB integrates two independent LVDS drivers and two LVDS receivers in one monolithic CMOS IC. Each driver accepts 3 V LVTTL/LVCMOS inputs and converts them to current-mode LVDS outputs (250–450 mV differential voltage); each receiver accepts LVDS inputs (±100 mV threshold window) and outputs 3 V CMOS logic levels.
It implements AND-gated EN/EN control for simultaneous TRI-STATE of all four LVDS outputs, internal fail-safe biasing on receiver inputs to guarantee HIGH output on floating inputs, and flow-through signal path alignment (DIN→DOUT, RIN→ROUT) enabling matched trace lengths and common-mode noise rejection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | +3.0 V to +3.6 V - supports standard 3.3 V rail with ±10% tolerance; static IDD = 21–35 mA. |
| Data Rate | Up to 400 Mbps - enables 200 MHz clocked serial links (fMAX = 250 MHz) in imaging and display timing applications. |
| Driver Skew | 50 ps typical channel-to-channel - ensures <0.5 ns skew between DOUT1 and DOUT2 paths for synchronized dual-channel transmission. |
| Receiver Threshold | VTH = −15 to +35 mV, VTL = −100 to −15 mV - provides robust noise margin against EMI in noisy industrial environments. |
| Fail-Safe Bias | Internal pull-up/pull-down on RIN+ and RIN− - guarantees ROUT = HIGH when receiver inputs are open or unterminated. |
| TRI-STATE Control | AND-gated EN/EN pins - disables all LVDS outputs simultaneously, reducing supply current to 15–25 mA in idle state. |
| Operating Temp | −40°C to +85°C - qualified for industrial-grade embedded systems without derating. |
Pinout & Package
TSSOP-16 (PW0016A) package, 4.4 mm × 5.0 mm body, 1.2 mm max height, 0.65 mm pitch, lead finish Sn, MSL Level-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4 | RIN− | Inverting LVDS receiver input; internal 12 µA pull-down current source enables fail-safe HIGH output on open inputs. |
| 2, 3 | RIN+ | Non-inverting LVDS receiver input; internal 12 µA pull-up current source complements RIN− for common-mode bias at ~1.2 V. |
| 5, 8 | DOUT− | Inverting LVDS driver output; requires 100 Ω termination to generate valid 250–450 mV differential swing. |
| 6, 7 | DOUT+ | Non-inverting LVDS driver output; current-mode output must be terminated to convert IOUT to VOD. |
| 9, 16 | EN / EN | AND-gated enable inputs; both must be HIGH to activate LVDS outputs; internal pull-downs ensure default disable on power-up. |
| 10, 11 | DIN | LVTTL/LVCMOS driver input; accepts 0–3.3 V logic; internal pull-down ensures LOW default if unconnected. |
| 12 | VDD | +3.3 V supply pin; requires local 0.1 µF + 0.001 µF ceramic decoupling per TI layout guidelines. |
| 13 | GND | Ground reference for all analog and digital circuitry; must connect to low-impedance ground plane. |
| 14, 15 | ROUT | LVCMOS receiver output; drives 3 V logic loads with VOH ≥ 2.7 V (IOH = −0.4 mA), VOL ≤ 0.25 V (IOL = 2 mA). |
Key Features
| Feature | Design Value |
|---|---|
| Flow-through pinout | Input (DIN/RIN) and output (DOUT/ROUT) signals aligned on opposite sides - enables straight PCB trace routing with minimal crosstalk and matched differential pair lengths. |
| Internal fail-safe biasing | Guarantees ROUT = HIGH when RIN+ or RIN− is floating - eliminates need for external bias resistors in point-to-point configurations. |
| Low-power TRI-STATE | Reduces IDD from 35 mA to 25 mA when disabled - critical for power-constrained portable and battery-backed industrial modules. |
| LVDS compliance | Fully conforms to TIA/EIA-644-A standard - ensures interoperability with industry-standard LVDS transceivers and cables. |
| Industrial temperature range | Validated operation from −40°C to +85°C - suitable for factory automation controllers, medical imaging front-ends, and outdoor kiosks. |
Applications
| Machine Vision Interface | Embedded Display Link |
|---|---|
|
Use Scenario: High-speed pixel data transmission from CMOS image sensor to FPGA-based frame grabber over 15 cm PCB traces. IC Role / Device Role / Timing Role: Dual LVDS driver converts parallel 8-bit sensor data into two serialized LVDS lanes; receiver recovers clock/data on host side. Use Value: 400 Mbps capability supports 60 fps @ 1080p; 50 ps skew preserves timing integrity across dual-lane capture. |
Use Scenario: Connecting LCD timing controller to panel driver IC in industrial HMI display using twisted-pair cable. IC Role / Device Role / Timing Role: DS90LV049TMTX/NOPB acts as bidirectional bridge: driver sends control signals, receiver returns status feedback. Use Value: Fail-safe biasing prevents spurious commands during hot-plug events; flow-through layout minimizes EMI-induced jitter. |
| Industrial Camera Backplane | Test Equipment Data Bus |
|
Use Scenario: Interconnecting multiple camera modules to central processing unit via backplane with 100 Ω differential impedance. IC Role / Device Role / Timing Role: Each DS90LV049TMTX/NOPB handles one camera's LVDS video stream and sync signals (HSYNC/VSYNC). Use Value: Matched propagation delays (<2 ns) and channel skew (<0.5 ns) ensure deterministic timing across multi-camera synchronization. |
Use Scenario: High-fidelity digital stimulus/response path in automated test equipment requiring sub-nanosecond edge fidelity. IC Role / Device Role / Timing Role: Driver transmits precise pattern data; receiver captures response with <3.5 ns propagation delay and <0.4 ns pulse skew. Use Value: Low 0.2–1.0 ns rise/fall times preserve signal integrity; TRI-STATE allows dynamic bus sharing without contention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LVDS transceiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN65LVDS32DR | Single-channel LVDS receiver only (no driver); 3.3 V supply; 400 Mbps rated; no EN control or fail-safe bias. | Requires separate LVDS driver IC; lacks integrated dual-function capability and flow-through layout. | Select when only receive functionality is needed and board space permits discrete driver/receiver partitioning. |
| DS90LV047ATMXT | Dual LVDS driver only (no receiver); identical pinout and electrical specs except missing RIN/ROUT pins. | Cannot perform bidirectional communication; requires companion receiver IC for full link implementation. | Choose when system already includes dedicated LVDS receivers and only additional driver capacity is required. |
Compared with SN65LVDS32DR and DS90LV047ATMXT, the DS90LV049TMTX/NOPB uniquely integrates matched driver-receiver pairs in one TSSOP-16 package with fail-safe biasing and AND-gated enable-reducing component count, PCB area, and interconnect complexity in compact industrial interconnects.
Availability
DS90LV049TMTX/NOPB is available at Aetrix Electronics and suitable for industrial imaging, embedded display interfaces, and test equipment requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for DS90LV049TMTX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-speed interface solutions, with decades of expertise in LVDS, SerDes, and industrial-grade signal conditioning ICs.
The DS90LV049TMTX/NOPB belongs to TI's LVDS transceiver product line, engineered specifically for noise-immune, low-power, high-speed point-to-point data links in factory automation, medical imaging, and instrumentation systems.
FAQ
What is the maximum data rate supported by the DS90LV049TMTX/NOPB?
The DS90LV049TMTX/NOPB supports up to 400 Mbps switching rates, corresponding to a maximum operating frequency of 250 MHz under specified conditions (VDD = 3.3 V, TA = −40°C to +85°C). This is validated by differential propagation delay (≤2 ns), rise/fall time (≤1 ns), and fMAX test criteria including duty cycle and output voltage thresholds.
Does the DS90LV049TMTX/NOPB require external termination resistors?
Yes - the DS90LV049TMTX/NOPB drivers are current-mode LVDS outputs and require a 100 Ω termination resistor across DOUT+ and DOUT− to generate the specified 250–450 mV differential output voltage (VOD). TI recommends placing the resistor within 12 mm of the receiver inputs to minimize stub length and maintain signal integrity.
How does the fail-safe biasing work on the DS90LV049TMTX/NOPB receiver inputs?
The DS90LV049TMTX/NOPB incorporates internal 12 µA pull-up on RIN+ and 12 µA pull-down on RIN−, establishing a nominal 1.2 V common-mode bias. When inputs are open or unterminated, this forces the receiver output ROUT to a stable HIGH state - eliminating false triggering and removing the need for external bias resistors in most point-to-point applications.
What is the function of the EN and EN pins on the DS90LV049TMTX/NOPB?
The EN and EN pins are AND-gated enable controls shared across all four LVDS outputs (DOUT1+, DOUT1−, DOUT2+, DOUT2−). Both must be driven HIGH to enable driver outputs; either LOW places all outputs in high-impedance TRI-STATE mode. Internal pull-downs ensure safe default disable at power-up, preventing bus contention.
Is the DS90LV049TMTX/NOPB compatible with 5 V logic systems?
No - the DS90LV049TMTX/NOPB is a 3.3 V-only device. Its LVCMOS inputs (DIN, EN, EN) accept 0–3.3 V logic levels, and its LVCMOS outputs (ROUT) swing 0–3.3 V. Driving DIN from 5 V logic risks exceeding absolute maximum input voltage (VDD + 0.3 V = 3.6 V), potentially damaging the IC. Level-shifting is required for 5 V system integration.
DS90LV049TMTX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Transceiver
- Protocol:
- LVDS
- Number of Drivers/Receivers:
- 2/2
- Duplex:
- Full
- Receiver Hysteresis:
- -
- Data Rate:
- 400Mbps
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
DS90LV049TMTX/NOPB FAQ
1.How can I place an order for DS90LV049TMTX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90LV049TMTX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90LV049TMTX/NOPB reliable?
The price and inventory of DS90LV049TMTX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90LV049TMTX/NOPB is usually 5 days.
3.What payment methods are accepted for DS90LV049TMTX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90LV049TMTX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90LV049TMTX/NOPB?
DS90LV049TMTX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90LV049TMTX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90LV049TMTX/NOPB?
For technical support, including DS90LV049TMTX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90LV049TMTX/NOPB requirements.
6.How does Aetrix verify that DS90LV049TMTX/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90LV049TMTX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90LV049TMTX/NOPB meets industry standards.
7.What is the process for return or replacement of DS90LV049TMTX/NOPB?
All DS90LV049TMTX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90LV049TMTX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90LV049TMTX/NOPB part is unused and in its original packaging.
Return procedure for DS90LV049TMTX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90LV049TMTX/NOPB Tags
-
ATA6561-GAQW-N
Microchip Technology
-
ATA6561-GBQW-N
Microchip Technology
-
AM26LS32ACDR
Texas Instruments
-
SP485CN-L/TR
MaxLinear, Inc.
-
SP485EN-L/TR
MaxLinear, Inc.
-
SP485EEN-L/TR
MaxLinear, Inc.
-
SP485ECN-L/TR
MaxLinear, Inc.
-
THVD1400DR
Texas Instruments
-
AM26C31IDR
Texas Instruments
-
TLIN1021ADRQ1
Texas Instruments
-
MAX232IDR
Texas Instruments
-
AM26C32IDR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
