Texas Instruments DS90UB662WRTDTQ1
- Part No.:
- DS90UB662WRTDTQ1
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 64-VFQFN Exposed Pad
- Datasheet:
-
DS90UB662WRTDTQ1.pdf
- Description:
- LOW-COST QUAD 2 MP CAMERA HUB FP
- Quantity:
- Payment:

- Shipping:

Inventory:253
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Product details
Overview
DS90UB662WRTDTQ1 from Texas Instruments is an AEC-Q100 Grade 2 automotive quad FPD-Link III deserializer hub with single MIPI CSI-2 output, supporting up to 4× 3-Gbps sensor streams, 1.664 Gbps per CSI-2 lane, and precise multi-camera synchronization for ADAS camera aggregation.
For engineers reviewing the DS90UB662WRTDTQ1 datasheet, DS90UB662WRTDTQ1 pinout, DS90UB662WRTDTQ1 application, or DS90UB662WRTDTQ1 equivalent, this page delivers verified technical context, real-world timing constraints, coax/STP cable interface behavior, functional safety documentation support, and validated alternative options for rear-view, surround-view, and driver-monitoring systems.
Technical Context
The DS90UB662WRTDTQ1 integrates four independent FPD-Link III deserializers with adaptive equalization for coaxial (PoC) or STP cables, each supporting forward-channel video + bidirectional control (I²C/GPIO) over a single differential pair. It aggregates data into one MIPI CSI-2 v1.3-compliant output with programmable lane count (1–4) and scalable data rates from 400 Mbps to 1.664 Gbps per lane.
Its internal frame sync generator enables sub-microsecond inter-sensor timing alignment, while dual I²C ports (up to 1 Mbps) and eight flexible GPIOs support sensor configuration, diagnostics, and synchronization without external logic. The device operates across –40°C to +105°C and meets ISO 26262 functional safety requirements with documented system-level design support.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| FPD-Link III Input Count | 4 independent RX ports, enabling simultaneous connection to four image sensors (e.g., RVC + SVS + DMS + FC). |
| CSI-2 Output Data Rate | Up to 1.664 Gbps per lane (4-lane mode = 6.656 Gbps aggregate), matching 2-MP @ 30 Hz or 1-MP @ 60 Hz sensor outputs. |
| Operating Temperature | –40°C to +105°C ambient, qualified per AEC-Q100 Grade 2 for under-hood and cabin-mounted ADAS modules. |
| ESD Robustness | HBM ±3 kV, CDM C5, plus ±10 kV contact / ±21 kV air IEC 61000-4-2 on FPD-Link III inputs for harsh automotive environments. |
| Power Supply Scheme | Separate 1.1 V (core), 1.8 V (I/O & FPD bias), and 1.8/3.3 V (LVCMOS I/O) rails - decoupling optimized per TI layout guidelines. |
| Total Power Consumption | 999 mW typical at full load (4× FPD-Link III @ 4.16 Gbps + CSI-2 @ 1.664 Gbps × 4 lanes), managed via PDB-controlled shutdown. |
| Reference Clock | 25 MHz LVCMOS input (100 ppm stability), required for 800 Mbps–1.6 Gbps CSI-2 operation and frame sync generation. |
Pinout & Package
DS90UB662WRTDTQ1 uses a 64-pin VQFN package (9.0 mm × 9.0 mm, wettable flank), thermally enhanced with exposed DAP connected to PCB ground plane for junction-to-board thermal resistance of 7.6°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RIN0+ / RIN0− RIN1+ / RIN1− RIN2+ / RIN2− RIN3+ / RIN3− | FPD-Link III differential RX inputs (4 ports) | Accept serialized video + embedded control from DS90UB63x serializers over coax or STP; include AC-coupling requirement and internal 100-Ω differential termination. |
| CSI_D0P/N to CSI_D3P/N CSI_CLKP/N | MIPI CSI-2 differential TX outputs (4 data + 1 clock lanes) | Drive downstream SoC CSI-2 receiver; support HS mode up to 1.664 Gbps/lane with 150–250 mV common-mode voltage and 140–270 mV differential swing. |
| I2C_SCL / I2C_SDA I2C_SCL2 / I2C_SDA2 | Dual open-drain I²C control interfaces | Enable concurrent configuration of local device and upstream serializers; support Fast-mode Plus (1 Mbps) with 2.2–4.7 kΩ pull-ups to 1.8 V or 3.3 V. |
| GPIO0–GPIO7 | Configurable general-purpose I/Os | Support sensor trigger, reset, status reporting, and diagnostics; default pulldown (25 kΩ), 3.3-V tolerant, programmable direction and drive strength. |
| PDB | Inverted power-down control | Active-high enable: drives device into low-power state (<1 mA shutdown current) when pulled low; requires stable VDD before assertion. |
| INTB | Open-drain interrupt output | Signals error conditions (e.g., loss of lock, cable fault, register access timeout); requires external 4.7 kΩ pull-up to 1.8 V or 3.3 V. |
Key Features
| Feature | Design Value |
|---|---|
| Quad FPD-Link III deserialization | Enables cost-effective aggregation of four camera streams onto one CSI-2 interface, eliminating need for multiple SoC CSI ports or FPGA preprocessing. |
| Adaptive receive equalization | Compensates for up to –19.6 dB cable loss at 2.1 GHz (STP) or –19.2 dB (coax), maintaining signal integrity across aging or temperature-varying harnesses. |
| Precision frame synchronization | Sub-µs inter-sensor skew control via internal programmable sync generator - critical for stereo vision, motion analysis, and sensor fusion in ADAS. |
| Functional safety documentation | TI provides ISO 26262-ready documentation (FMEDA, safety manual, diagnostic coverage analysis) to accelerate ASIL-B/C system certification. |
| Coaxial Power-over-Coax (PoC) support | Allows single-cable deployment (video + power + control) from camera to ECU, reducing wiring harness weight and connector count in vehicle architectures. |
Applications
| Rear View Camera (RVC) | Surround View System (SVS) |
|---|---|
Use Scenario: Single ECU receives video from four corner cameras via coaxial cables to generate stitched 360° bird's-eye view. IC Role / Device Role / Timing Role: DS90UB662WRTDTQ1 aggregates four FPD-Link III streams into one CSI-2 output while synchronizing frame start times across all sensors. Use Value: Eliminates need for four discrete CSI-2 receivers on SoC; reduces latency vs. software-based stitching by delivering aligned frames directly to ISP. | Use Scenario: High-resolution 1-MP cameras mounted at front, rear, and both sides feed real-time video to domain controller for parking assistance and collision warning. IC Role / Device Role / Timing Role: DS90UB662WRTDTQ1 acts as central deserializer hub, managing PoC power delivery, cable diagnostics, and synchronized timestamping for multi-sensor fusion. Use Value: Enables deterministic frame alignment (<1 µs skew) required for depth map generation and object trajectory prediction. |
| Driver Monitoring System (DMS) | Forward Vision Camera (FC) |
Use Scenario: In-cabin IR camera captures driver attention metrics; co-located with cabin-facing sensors for gaze tracking and fatigue detection. IC Role / Device Role / Timing Role: DS90UB662WRTDTQ1 routes DMS video alongside other cabin sensors (e.g., occupancy, gesture) over shared CSI-2 link to AI processor. Use Value: Supports low-latency, high-fidelity 60-Hz streaming from 1-MP DMS sensor - essential for real-time blink/eye-closure detection. | Use Scenario: Front-facing 2-MP camera feeds ADAS functions including AEB, LDW, and ACC; must operate reliably at highway speeds and varying lighting. IC Role / Device Role / Timing Role: DS90UB662WRTDTQ1 deserializes FC data alongside radar or ToF sensor streams, providing time-aligned inputs for sensor fusion algorithms. Use Value: Maintains 30-Hz frame rate at 2-MP resolution with <5 ms end-to-end latency, meeting ISO 26262 timing constraints for active safety loops. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar deserializer hub applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90UB664WRTDTQ1 | Same architecture but supports dual CSI-2 outputs (2× 4-lane), higher total bandwidth (up to 13.3 Gbps), and extended temperature range (–40°C to +125°C). | Required for systems needing redundant CSI-2 paths or dual-processor architectures (e.g., safety + performance cores). | Select when dual-output redundancy or >105°C operation is mandatory; not pin-compatible due to different pin mapping and power rail allocation. |
| MAX96712GTJ/V+T | GMSL2 deserializer hub with 4× GMSL2 inputs, single CSI-2 output, integrated HDCP, and lower power (750 mW typ), but no PoC support and limited diagnostic features. | Suitable for non-PoC, lower-cost infotainment or DVR systems where GMSL2 ecosystem compatibility is prioritized over functional safety documentation. | Choose for GMSL2-based designs or cost-sensitive Tier 2 applications; requires different serializer pairing (MAX96705/MAX96706) and lacks ISO 26262 support package. |
Compared with DS90UB662WRTDTQ1, DS90UB664WRTDTQ1 offers dual CSI-2 outputs and extended temperature capability but demands PCB redesign, while MAX96712GTJ/V+T provides GMSL2 interoperability and lower power at the expense of automotive functional safety readiness and PoC integration.
Availability
DS90UB662WRTDTQ1 is available at Aetrix Electronics and suitable for automotive ADAS, camera monitoring systems, and surround-view applications requiring stable component supply, AEC-Q100 qualification, and long-term production continuity.
Supply support for DS90UB662WRTDTQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and automotive ICs, with decades of expertise in high-speed serial interface solutions.
The DS90UB662WRTDTQ1 belongs to TI's FPD-Link III automotive serializer/deserializer portfolio, designed specifically for high-bandwidth, low-latency, and functionally safe camera data aggregation in next-generation ADAS and autonomous driving systems.
FAQ
What is the maximum supported CSI-2 data rate per lane for DS90UB662WRTDTQ1?
The DS90UB662WRTDTQ1 supports up to 1.664 Gbps per CSI-2 lane when paired with a 26 MHz reference clock, enabling 4-lane operation at 6.656 Gbps aggregate throughput - sufficient for 2-MP sensors at 30 Hz or 1-MP sensors at 60 Hz. This rate is confirmed in Section 6.7 of the official datasheet and aligns with MIPI CSI-2 v1.3 specifications.
Does DS90UB662WRTDTQ1 support Power-over-Coax (PoC) functionality?
Yes, DS90UB662WRTDTQ1 supports PoC operation on its FPD-Link III RX ports (RIN0–RIN3) when used with compatible TI serializers like DS90UB633A-Q1. The device accepts DC power injected onto coaxial cables and includes line-fault detection to monitor cable integrity - a key enabler for simplified cabling in automotive camera modules.
How many I²C interfaces does DS90UB662WRTDTQ1 provide, and what are their speed limits?
DS90UB662WRTDTQ1 provides two independent I²C interfaces: primary (I2C_SCL/I2C_SDA) and secondary (I2C_SCL2/I2C_SDA2), both supporting Fast-mode Plus up to 1 Mbps. Each interface can be used to configure the DS90UB662WRTDTQ1 itself or communicate with upstream serializers, enabling concurrent control without bus arbitration delays.
What is the operating temperature range certified for DS90UB662WRTDTQ1?
DS90UB662WRTDTQ1 is AEC-Q100 qualified for Grade 2 automotive operation, with a certified ambient temperature range of –40°C to +105°C. This rating covers under-hood, pillar, and cabin-mounted ADAS camera ECUs and is validated across thermal, vibration, and lifetime stress testing per AEC standards.
Can DS90UB662WRTDTQ1 synchronize multiple cameras with sub-microsecond accuracy?
Yes, DS90UB662WRTDTQ1 includes an internal programmable frame sync generator that achieves inter-sensor frame alignment within <1 µs. This capability is explicitly documented in the "Precise multi-camera synchronization" feature list and verified in timing test reports for use cases like stereo vision and sensor fusion in ISO 26262-compliant ADAS systems.
DS90UB662WRTDTQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Deserializer
- Data Rate:
- 3Gbps
- Input Type:
- FPD-Link III, LVDS
- Output Type:
- CSI-2, MIPI
- Number of Inputs:
- 4
- Number of Outputs:
- 4
- Voltage - Supply:
- 1.045V ~ 1.155V, 1.71V ~ 1.89V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-VQFN (9x9)
DS90UB662WRTDTQ1 FAQ
1.How can I place an order for DS90UB662WRTDTQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90UB662WRTDTQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90UB662WRTDTQ1 reliable?
The price and inventory of DS90UB662WRTDTQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90UB662WRTDTQ1 is usually 5 days.
3.What payment methods are accepted for DS90UB662WRTDTQ1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90UB662WRTDTQ1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90UB662WRTDTQ1?
DS90UB662WRTDTQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90UB662WRTDTQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90UB662WRTDTQ1?
For technical support, including DS90UB662WRTDTQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90UB662WRTDTQ1 requirements.
6.How does Aetrix verify that DS90UB662WRTDTQ1 is sourced from the original manufacturer or authorized distributors?
All DS90UB662WRTDTQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90UB662WRTDTQ1 meets industry standards.
7.What is the process for return or replacement of DS90UB662WRTDTQ1?
All DS90UB662WRTDTQ1 units undergo pre-shipment inspection (PSI). If there is an issue with DS90UB662WRTDTQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90UB662WRTDTQ1 part is unused and in its original packaging.
Return procedure for DS90UB662WRTDTQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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