My Inquiry
My Account
Texas Instruments DS90UB901QSQ/NOPB
- Part No.:
- DS90UB901QSQ/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 32-WFQFN Exposed Pad
- Datasheet:
-
DS90UB901QSQ/NOPB.pdf
- Description:
- IC SER/DESER 10-43MHZ 16B 32WQFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,038
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90UB901QSQ/NOPB from Texas Instruments is an automotive-grade FPD-Link III serializer IC that converts 14-bit parallel image data (YUV/RGB) and sync signals (HSYNC/VSYNC) into a high-speed serial stream over a single differential pair. It supports 10–43 MHz pixel clock, delivers up to 688 Mbps throughput, embeds clock via DC-balanced coding, and integrates bidirectional I²C-compatible control channel for camera-to-ECU communication in rear-view systems.
For engineers reviewing the DS90UB901QSQ/NOPB datasheet, DS90UB901QSQ/NOPB pinout, DS90UB901QSQ/NOPB application, or DS90UB901QSQ/NOPB equivalent, this page provides verified technical context, validated pin functions, confirmed AEC-Q100 Grade 2 compliance, real-world automotive vision use cases, and two rigorously cross-checked alternative serializers with documented functional and interface differences.
Technical Context
The DS90UB901QSQ/NOPB implements embedded-clock FPD-Link III encoding with 8b/10b-like DC balancing to enable AC-coupled interconnects over shielded twisted-pair up to 10 meters. Its CML transmitter drives DOUT+/DOUT− with programmable equalization support on the deserializer side, and its internal PLL locks without external reference clock.
It features a dual-mode bidirectional control channel supporting both master (SCL generation) and slave (SCL acceptance) I²C operation, plus integrated CRC for payload integrity checking and LOCK reporting for link status monitoring. The serializer includes GPIO[5:0], PDB power-down control, and MODE/ID[x]/RES configuration pins with defined pull-down/pull-up behavior.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| PCLK Range | 10–43 MHz: Supports standard automotive camera pixel clocks including 13.5 MHz (HD), 27 MHz (Full HD), and 43 MHz (WUXGA). |
| Data Throughput | 160–688 Mbps: Enables transmission of 14-bit RGB/YUV video + HSYNC/VSYNC + bidirectional control traffic over one differential pair. |
| Supply Voltage | 1.8 V ±5% (VDDn/VDDT/VDDCML/VDDD) and 1.8 V or 3.3 V ±10% (VDDIO): Dual-voltage I/O flexibility for interfacing with 1.8 V sensors or 3.3 V microcontrollers. |
| ESD Rating | IEC 61000-4-2 ≥±25 kV (air), ISO 10605 ≥±15 kV (air): Validated for harsh automotive environments with high electrostatic discharge risk. |
| Operating Temp | −40°C to +105°C: Qualified per AEC-Q100 Grade 2, enabling placement in camera modules exposed to under-hood or exterior thermal stress. |
| CRC Support | 16-bit payload with optional Cyclic Redundancy Check: Detects bit errors in transmitted image data without requiring blanking intervals. |
| Package | 32-pin WQFN (5 mm × 5 mm, RTV0032A): Compact surface-mount footprint with exposed DAP for thermal management in space-constrained camera housings. |
Pinout & Package
DS90UB901QSQ/NOPB uses a 32-pin WQFN package (5 mm × 5 mm, package code RTV0032A) with exposed thermal pad (DAP) requiring ≥9 vias to ground plane. Pin functions are validated per TI SNLS322E Rev. April 2013.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DIN[13:0] | Parallel data input bus | 14-bit LVCMOS inputs accepting YUV/RGB pixel data; each pin has internal pull-down for unused lanes. |
| HSYNC / VSYNC / PCLK | Timing signal inputs | Synchronous capture control: HSYNC/VSYNC define frame boundaries; PCLK edge (configurable via TRFB register) latches DIN data. |
| SCL / SDA | I²C bidirectional control bus | Open-drain pins requiring external pull-ups to VDDIO; support full-duplex remote configuration and status readback independent of video stream. |
| DOUT+ / DOUT− | FPD-Link III CML output | Differential CML outputs driving single twisted-pair cable; require AC coupling (100 nF) and 100 Ω termination at deserializer end. |
| PDB / MODE / ID[x] / RES | Configuration & control | PDB enables/disables device; MODE selects I²C master/slave; ID[x] sets device address; RES must be tied low per datasheet. |
| GPIO[5:0] | Configurable I/O | Six general-purpose pins-DIN[3:0]/GPIO[5:2] and GPIO[1:0]-individually assignable as inputs or outputs for camera-side signaling or diagnostics. |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional I²C control channel | Enables real-time camera register access, firmware updates, and diagnostic feedback over same cable carrying video-no separate control wiring needed. |
| Embedded clock with DC balance | Eliminates need for separate clock trace or reference clock on deserializer side; supports AC-coupled cabling for noise immunity and EMI reduction. |
| Programmable CRC integrity check | Verifies correctness of 16-bit serialized payload at deserializer; PASS pin asserts low on CRC error detection for immediate link health monitoring. |
| Remote wake-up capability | Serializer enters low-power standby when PDB = L and wakes on deserializer-initiated control channel activity-reducing camera module quiescent current. |
| Integrated CML termination | On-chip 80–120 Ω differential termination reduces external component count and improves signal integrity on high-speed serial output. |
Applications
| Rear-View Camera System | Lane Departure Warning (LDW) |
|---|---|
Use Scenario: High-resolution backup camera mounted on vehicle rear bumper transmitting live video to infotainment display. IC Role / Device Role / Timing Role: DS90UB901QSQ/NOPB serializes 14-bit RGB image data and sync signals for transmission over 6–8 m shielded twisted-pair cable to host ECU. Use Value: Single-cable solution eliminates skew between parallel data/clock lines, reduces connector size by >50%, and meets ISO 10605 ESD requirements for exterior mounting. | Use Scenario: Forward-facing camera detecting lane markings and triggering driver alerts during unintended lane drift. IC Role / Device Role / Timing Role: DS90UB901QSQ/NOPB captures and serializes high-frame-rate YUV video with precise timing (PCLK = 27 MHz) for real-time processing in ADAS ECU. Use Value: Embedded clock ensures deterministic latency (<6.4 ns + 12 ns typical delay); CRC validation guarantees pixel integrity critical for object classification accuracy. |
| Parking Assistance System | Blind Spot Detection (BSD) |
Use Scenario: Multi-camera system using side-mounted cameras to generate 360° surround-view display with dynamic guidance overlays. IC Role / Device Role / Timing Role: DS90UB901QSQ/NOPB interfaces with CMOS image sensor, formats parallel data, and transmits synchronized video streams over dedicated FPD-Link III links. Use Value: Six GPIOs enable direct connection to proximity sensors or LED indicators; LOCK pin confirms stable CDR lock before video rendering begins. | Use Scenario: Mirror-mounted or fender-integrated camera monitoring adjacent lanes for vehicles entering blind zones. IC Role / Device Role / Timing Role: DS90UB901QSQ/NOPB handles low-latency video transport (≤1 ms total link delay) while supporting bidirectional I²C for auto-exposure and white balance tuning. Use Value: Programmable receive equalization on deserializer compensates for 10 m cable loss; spread-spectrum clocking (SSCG) reduces EMI emissions in RF-sensitive zones. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPD-Link III serializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90UB913AQRTVRQ1 | Supports higher PCLK (up to 85 MHz), adds MIPI CSI-2 output option, requires external 27 MHz reference clock for some modes. | Targeted for higher-resolution ADAS cameras (e.g., 4 MP @ 30 fps); lacks native 1.8 V/3.3 V dual-VDDIO flexibility. | Choose DS90UB913AQRTVRQ1 when bandwidth exceeds 688 Mbps or MIPI compatibility is required; retain DS90UB901QSQ/NOPB for cost-sensitive 1080p systems with no reference clock. |
| MAX96705GTJ+T | Offers GMSL2 compatibility, supports longer reach (15 m), includes built-in HDCP engine and AES encryption. | Designed for premium infotainment and digital cockpit applications requiring content protection and extended cable length. | Choose MAX96705GTJ+T when HDCP/AES security or >10 m cable run is mandatory; DS90UB901QSQ/NOPB remains optimal for standard AEC-Q100-compliant vision systems without encryption needs. |
Compared with DS90UB913AQRTVRQ1 and MAX96705GTJ+T, DS90UB901QSQ/NOPB provides the most cost-effective, reference-clock-free FPD-Link III serialization for 1080p automotive cameras operating within 10 m, with full I²C configurability and proven thermal performance in compact WQFN packaging.
Availability
DS90UB901QSQ/NOPB is available at Aetrix Electronics and suitable for rear-view camera systems, lane departure warning modules, and parking assistance ECUs requiring stable component supply, AEC-Q100 qualification, and long-term automotive lifecycle support.
Supply support for DS90UB901QSQ/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and automotive electronics, with decades of experience delivering high-reliability interface solutions.
The DS90UB901QSQ/NOPB belongs to TI's FPD-Link III automotive serializer family, engineered specifically for robust, low-latency video transport in safety-critical driver-assistance systems operating across extreme temperature and EMI environments.
FAQ
What is the maximum supported cable length for DS90UB901QSQ/NOPB?
The DS90UB901QSQ/NOPB is characterized to drive up to 10 meters of shielded twisted-pair cable under standard conditions. This assumes proper AC coupling (100 nF), 100 Ω termination, and use with the companion DS90UB902Q deserializer featuring programmable receive equalization to compensate for frequency-dependent loss. Longer runs require validation with actual cable type and environmental conditions.
Does DS90UB901QSQ/NOPB require an external reference clock?
No, DS90UB901QSQ/NOPB does not require an external reference clock. It uses embedded clock technology where timing information is encoded within the serial data stream, allowing the deserializer to recover clock and data simultaneously. This eliminates clock distribution complexity and skew issues in automotive camera modules.
How is the I²C bidirectional control channel implemented on DS90UB901QSQ/NOPB?
The DS90UB901QSQ/NOPB implements the bidirectional control channel using open-drain SCL and SDA pins compliant with standard I²C timing. It supports both master mode (generating SCL) and slave mode (accepting external SCL), configurable via the MODE pin. Communication occurs independently of video transmission, enabling real-time register access and diagnostics without interrupting the video stream.
What GPIO capabilities does DS90UB901QSQ/NOPB provide?
DS90UB901QSQ/NOPB provides six programmable GPIOs: DIN[3:0]/GPIO[5:2] (pins 20–17) and GPIO[1:0] (pins 16–15). Each can be individually configured as input or output via internal registers. They support camera-side functions such as LED control, sensor reset signaling, or diagnostic status indication-enabling flexible integration without additional logic.
Is DS90UB901QSQ/NOPB compatible with 3.3 V I/O interfaces?
Yes, DS90UB901QSQ/NOPB supports 3.3 V LVCMOS I/O through its VDDIO supply pin, which accepts 3.0–3.6 V. All parallel inputs (DIN[13:0], HSYNC, VSYNC, PCLK), GPIOs, and control pins (SCL/SDA, MODE, PDB) operate at either 1.8 V or 3.3 V depending on VDDIO voltage, providing seamless interfacing with both modern low-voltage image sensors and legacy 3.3 V microcontrollers.
DS90UB901QSQ/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 32-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Serializer
- Data Rate:
- 688Mbps
- Input Type:
- LVCMOS
- Output Type:
- FPD-Link III, LVDS
- Number of Inputs:
- 14
- Number of Outputs:
- 1
- Voltage - Supply:
- 1.71V ~ 1.89V, 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-WQFN (5x5)
DS90UB901QSQ/NOPB FAQ
1.How can I place an order for DS90UB901QSQ/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90UB901QSQ/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90UB901QSQ/NOPB reliable?
The price and inventory of DS90UB901QSQ/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90UB901QSQ/NOPB is usually 5 days.
3.What payment methods are accepted for DS90UB901QSQ/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90UB901QSQ/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90UB901QSQ/NOPB?
DS90UB901QSQ/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90UB901QSQ/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90UB901QSQ/NOPB?
For technical support, including DS90UB901QSQ/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90UB901QSQ/NOPB requirements.
6.How does Aetrix verify that DS90UB901QSQ/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90UB901QSQ/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90UB901QSQ/NOPB meets industry standards.
7.What is the process for return or replacement of DS90UB901QSQ/NOPB?
All DS90UB901QSQ/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90UB901QSQ/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90UB901QSQ/NOPB part is unused and in its original packaging.
Return procedure for DS90UB901QSQ/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90UB901QSQ/NOPB Tags
-
SN65HVS880PWPR
Texas Instruments
-
SN65HVS882PWPR
Texas Instruments
-
FIN3386MTDX
onsemi
-
FIN3385MTDX
onsemi
-
SN65LV1023ARHBR
Texas Instruments
-
SN65LV1023ADBR
Texas Instruments
-
SN65LV1224BDBR
Texas Instruments
-
SN65LVDS93ADGGR
Texas Instruments
-
SN65LVDS93DGGR
Texas Instruments
-
TDES954RGZT
Texas Instruments
-
SN65LV1224BRHBT
Texas Instruments
-
DS90UB914QSQE/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
