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Texas Instruments DS90UB902QSQ/NOPB
- Part No.:
- DS90UB902QSQ/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 40-WFQFN Exposed Pad
- Datasheet:
-
DS90UB902QSQ/NOPB.pdf
- Description:
- IC SER/DESER 10-43MHZ 16B 40WQFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,968
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Product details
Overview
DS90UB902QSQ/NOPB from Texas Instruments is an automotive-grade FPD-Link III deserializer that converts high-speed serial data from a camera sensor into 14-bit parallel RGB/YUV video, horizontal/vertical sync, and pixel clock outputs. It operates at 10–43 MHz PCLK, supports up to 688 Mbps throughput over a single differential pair, includes embedded clock recovery with CRC error detection, and drives up to 10 meters of shielded twisted-pair cable. It is used in rear-view and lane-departure warning camera modules.
For engineers reviewing the DS90UB902QSQ/NOPB datasheet, DS90UB902QSQ/NOPB pinout, DS90UB902QSQ/NOPB application, or DS90UB902QSQ/NOPB equivalent, key selection criteria include its AEC-Q100 Grade 2 qualification, bidirectional I²C-compatible control channel, programmable receive equalization for long-cable compensation, LOCK status reporting, and integrated CML termination - all critical for automotive vision system design and validation.
Technical Context
The DS90UB902QSQ/NOPB implements a CDR-based deserialization architecture with adaptive receive equalization to compensate for frequency-dependent loss across shielded twisted-pair media up to 10 m. Its PLL locks to the embedded clock within 10 ms after power-up or wake-up, and it reconstructs a low-jitter PCLK (±250 ps period jitter at 43 MHz) with optional spread-spectrum output to reduce EMI.
It integrates a full bidirectional control channel compliant with I²C timing (100 kHz), supporting master/slave mode selection via MODE pin and device addressing via ID[x] resistor network. The deserializer provides 14-bit parallel LVCMOS outputs (ROUT[13:0], HSYNC, VSYNC, PCLK), two GPIOs, LOCK status, PASS/CRC error flag, BIST enable, and test ports (CMLOUTP/N) for signal integrity validation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| PCLK Range | 10–43 MHz - defines supported image sensor resolution and frame rate; enables VGA to 1 MP at 30–60 fps. |
| Data Throughput | 160–688 Mbps - determined by PCLK × 16-bit payload; supports 14-bit video + CRC + control overhead. |
| Input Interface | CML differential pair (RIN+/RIN−) - AC-coupled, 100 Ω terminated; enables robust noise immunity over long cables. |
| Output Interface | 14-bit LVCMOS parallel bus (ROUT[13:0]) + HSYNC/VSYNC/PCLK - directly interfaces to SoC or FPGA video input logic. |
| Supply Voltage | 1.8 V ±5% (VDDn, VDDPLL, VDDR, VDDCML) and 1.8/3.3 V ±10% (VDDIO) - dual-voltage flexibility for mixed-signal system integration. |
| Temperature Range | −40°C to +105°C - meets AEC-Q100 Grade 2 requirements for under-hood and cabin-mounted camera ECUs. |
| CRC Support | Enabled on 16-bit payload - detects bit errors in received video stream; PASS pin asserts low on CRC failure. |
Pinout & Package
DS90UB902QSQ/NOPB is housed in a 40-pin WQFN package (6 mm × 6 mm, RTA0040A), thermally enhanced with 16 vias to DAP ground. The exposed thermal pad (DAP) must be soldered to PCB ground plane for thermal and EMI performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ROUT[13:0] | LVCMOS parallel video/data outputs | 14-bit reconstructed pixel data bus; level-shifted to 1.8 V or 3.3 V per VDDIO setting. |
| HSYNC / VSYNC | LVCMOS sync outputs | Active-high timing signals synchronized to deserialized video stream; compatible with standard video interface timing. |
| PCLK | LVCMOS pixel clock output | Recovered clock with <250 ps period jitter at 43 MHz; edge polarity configurable via RRFB register. |
| RIN+ / RIN− | CML differential serial input | AC-coupled inputs with internal 100 Ω termination; support equalization tuning for cable loss compensation. |
| LOCK | LVCMOS lock status indicator | High = CDR/PLL locked and outputs stable; used for system-level link health monitoring and fault recovery. |
| PASS | LVCMOS CRC error flag | High = no CRC errors detected; low = at least one CRC mismatch occurred on received payload. |
| SCL / SDA | I²C bidirectional control bus | Open-drain, 100 kHz compliant; enables camera configuration, diagnostics, and firmware updates without dedicated wires. |
| GPIO[1:0] | Configurable general-purpose I/O | Individually programmable as input or output; usable for sideband signaling, LED control, or interrupt generation. |
| BISTEN | Built-in self-test enable input | Activates internal PRBS pattern generator and checker for production line or field link integrity validation. |
| PDB | Power-down control input | Low = ultra-low quiescent current (<1 µA); remote wake-up supported via incoming serial data edge. |
Key Features
| Feature | Design Value |
|---|---|
| FPD-Link III compliance | Single-pair serialization with embedded clock and DC-balanced coding - eliminates separate clock routing and enables AC-coupled interconnects. |
| Programmable receive equalization | Adjustable gain/filter settings compensate for up to 10 m of STP loss - maintains signal integrity without external equalizers. |
| Integrated CML termination | On-die 100 Ω differential termination - reduces component count, layout complexity, and impedance mismatch risk. |
| At-speed BIST with PASS output | Hardware-accelerated link validation using PRBS patterns - enables automated test during manufacturing or runtime diagnostics. |
| Spread-spectrum clocking (SSCG) | Configurable ±0.5% to ±2.0% deviation at 9–66 kHz - lowers EMI peak emissions for automotive EMC compliance. |
Applications
| Rear-View Camera System | Lane Departure Warning (LDW) |
|---|---|
Use Scenario: High-reliability video transmission from rear-facing camera to display or ADAS ECU through harness wiring. IC Role / Device Role / Timing Role: Deserializes FPD-Link III stream into parallel RGB/YUV video and timing signals for real-time display rendering. Use Value: Enables compact, lightweight cabling (single STP vs. multi-wire harness), reduces EMI susceptibility, and ensures CRC-verified video integrity for safety-critical display. | Use Scenario: Low-latency video feed from forward-facing camera to LDW algorithm processor. IC Role / Device Role / Timing Role: Provides precisely timed pixel clock and sync signals required for sub-pixel object detection and lane marking analysis. Use Value: Delivers <250 ps PCLK jitter at 43 MHz and <10 ms lock time - meeting real-time processing deadlines for ISO 17387-compliant LDW systems. |
| Parking Assistance Module | Blind Spot Detection (BSD) |
Use Scenario: Integration of multiple surround-view cameras into a central stitching ECU with minimal board space. IC Role / Device Role / Timing Role: Converts serialized camera streams into parallel video while sharing I²C bus for simultaneous camera parameter control. Use Value: Reduces interconnect layer count and connector size; supports up to 6 GPIOs for proximity sensor coordination and LED feedback control. | Use Scenario: High-speed video acquisition from side-mirror or fender-mounted cameras in harsh temperature environments. IC Role / Device Role / Timing Role: Performs robust deserialization over extended cable runs with adaptive equalization and AEC-Q100 Grade 2 thermal resilience. Use Value: Maintains link stability across −40°C to +105°C ambient and compensates for cable aging/temperature drift via programmable equalizer registers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPD-Link III deserializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90UB928QSQ/NOPB | Supports 16-bit payload with MIPI CSI-2 output instead of LVCMOS; higher max PCLK (85 MHz); includes HDCP support. | Targeted for next-gen ADAS SoCs requiring MIPI interface; not pin-compatible; requires different PCB layout and firmware adaptation. | Select when migrating to MIPI-based host processors and need higher bandwidth or content protection. |
| MAX96705GTJ/V+T | 10-bit deserializer with GMSL2 interface; lower power; integrated voltage regulators; different I²C address scheme and register map. | Used in cost-sensitive entry-level camera modules; lacks CRC and BIST features; supports shorter cable lengths (≤8 m). | Select for simplified supply architecture and GMSL2 ecosystem compatibility, accepting reduced diagnostic capability. |
Compared with DS90UB902QSQ/NOPB, DS90UB928QSQ/NOPB offers higher bandwidth and MIPI output but requires redesign, while MAX96705GTJ/V+T provides GMSL2 integration and lower power at the expense of CRC validation and longer-cable equalization - making DS90UB902QSQ/NOPB optimal for legacy LVCMOS-based automotive vision systems needing proven reliability and comprehensive diagnostics.
Availability
DS90UB902QSQ/NOPB is available at Aetrix Electronics and suitable for automotive rear-view camera systems, lane departure warning modules, and parking assistance ECUs requiring stable component supply across extended product lifecycles.
Supply support for DS90UB902QSQ/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies for automotive, industrial, and communications markets.
The DS90UB902QSQ/NOPB belongs to TI's FPD-Link III serializer/deserializer product line, engineered specifically for high-reliability, low-latency video transport in automotive vision systems - balancing bandwidth, diagnostics, and AEC-Q100 compliance.
FAQ
What is the primary function of the DS90UB902QSQ/NOPB in an automotive camera system?
The DS90UB902QSQ/NOPB serves as the deserializer in an FPD-Link III camera link, converting high-speed serial data from a remote camera sensor into parallel 14-bit video (ROUT[13:0]), sync signals (HSYNC/VSYNC), and a recovered pixel clock (PCLK). It enables reliable, low-skew video transport over a single shielded twisted-pair cable - a core requirement for rear-view, LDW, and surround-view systems. DS90UB902QSQ/NOPB also provides CRC error checking, LOCK status, and I²C-based camera control.
Does the DS90UB902QSQ/NOPB require an external reference clock?
No, the DS90UB902QSQ/NOPB does not require an external reference clock. It uses embedded clock technology to recover timing directly from the incoming FPD-Link III serial stream via its CDR circuitry. This eliminates clock distribution skew and simplifies system design - a key advantage over parallel or source-synchronous interfaces. DS90UB902QSQ/NOPB achieves PLL lock in ≤10 ms after power-up or wake-up with an active PCLK input.
How does the DS90UB902QSQ/NOPB handle long cable runs, and what is its maximum supported length?
The DS90UB902QSQ/NOPB supports up to 10 meters of shielded twisted-pair (STP) cable using programmable receive equalization to compensate for frequency-dependent attenuation. Its CML receiver includes adjustable gain and filter settings accessible via I²C registers, enabling optimization for varying cable types and lengths. DS90UB902QSQ/NOPB maintains link integrity under automotive EMI conditions and meets ISO 10605 and IEC 61000-4-2 ESD standards (≥±15 kV air, ≥±10 kV contact).
What diagnostic capabilities does the DS90UB902QSQ/NOPB provide for production testing and field operation?
The DS90UB902QSQ/NOPB includes built-in diagnostic features: a LOCK pin indicating CDR/PLL lock status, a PASS pin asserting low on CRC errors, and BISTEN-triggered at-speed built-in self-test using PRBS patterns. These allow hardware-level validation of link integrity during manufacturing burn-in or runtime health checks. DS90UB902QSQ/NOPB also provides CMLOUTP/CMLOUTN test ports for oscilloscope-based signal quality assessment without breaking the link.
Can the DS90UB902QSQ/NOPB interface directly with a 3.3 V microcontroller or FPGA?
Yes, the DS90UB902QSQ/NOPB supports dual I/O voltage operation: its LVCMOS outputs (ROUT[13:0], HSYNC, VSYNC, PCLK, GPIOs) can be powered from either 1.8 V or 3.3 V via the VDDIO supply pins (VDDIO1/2/3). When VDDIO is set to 3.3 V, outputs meet 3.3 V LVCMOS specifications (VOH ≥ 2.4 V, VOL ≤ 0.4 V at 4 mA load), ensuring direct compatibility with 3.3 V logic without level shifters. DS90UB902QSQ/NOPB maintains full functionality across both voltage modes.
DS90UB902QSQ/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 40-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Deserializer
- Data Rate:
- 688Mbps
- Input Type:
- FPD-Link III, LVDS
- Output Type:
- LVCMOS
- Number of Inputs:
- 1
- Number of Outputs:
- 14
- Voltage - Supply:
- 1.71V ~ 1.89V, 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-WQFN (6x6)
DS90UB902QSQ/NOPB FAQ
1.How can I place an order for DS90UB902QSQ/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90UB902QSQ/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90UB902QSQ/NOPB reliable?
The price and inventory of DS90UB902QSQ/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90UB902QSQ/NOPB is usually 5 days.
3.What payment methods are accepted for DS90UB902QSQ/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90UB902QSQ/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90UB902QSQ/NOPB?
DS90UB902QSQ/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90UB902QSQ/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90UB902QSQ/NOPB?
For technical support, including DS90UB902QSQ/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90UB902QSQ/NOPB requirements.
6.How does Aetrix verify that DS90UB902QSQ/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90UB902QSQ/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90UB902QSQ/NOPB meets industry standards.
7.What is the process for return or replacement of DS90UB902QSQ/NOPB?
All DS90UB902QSQ/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90UB902QSQ/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90UB902QSQ/NOPB part is unused and in its original packaging.
Return procedure for DS90UB902QSQ/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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