Texas Instruments DS90UB914QSQX/NOPB
- Part No.:
- DS90UB914QSQX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
DS90UB914QSQX/NOPB.pdf
- Description:
- IC SER/DES 10-100MHZ FPD 48WQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS90UB914QSQX/NOPB from Texas Instruments is an automotive-grade FPD-Link III deserializer IC for camera-to-ECU video links, supporting 10- or 12-bit pixel data at 10–100 MHz PCLK, bidirectional I²C-compatible control channel up to 400 kHz, and dual-input imager multiplexing (RIN0±/RIN1±). It delivers parallel LVCMOS outputs (ROUT[0:11]), HSYNC/VSYNC timing, and LOCK status reporting for ADAS front/rear/surround-view systems.
For engineers reviewing the DS90UB914QSQX/NOPB datasheet, DS90UB914QSQX/NOPB pinout, DS90UB914QSQX/NOPB application, or DS90UB914QSQX/NOPB equivalent, this page provides verified functional specifications, validated WQFN-48 package mapping, confirmed GPIO/GPO interoperability with DS90UB913Q-Q1, real-world ESD performance (≥±25 kV air), and precise PLL lock behavior under temperature-cycled operation.
Technical Context
The DS90UB914QSQX/NOPB implements embedded-clock DC-balanced encoding over a single shielded twisted-pair (STP), enabling AC-coupled interconnects up to 25 meters. Its adaptive equalizer dynamically compensates cable loss across frequency, while the 2:1 input MUX selects between two independent imagers - only one active at a time - with seamless switching controlled via SEL pin or register.
It integrates a 1.8-V PLL with LOCK output, programmable spread-spectrum clock generation (SSCG) on VDDSSCG, and built-in self-test (BIST) with PASS output. The bidirectional control channel operates independently of video blanking, supporting full-duplex I²C traffic at 400 kHz while maintaining sub-microsecond latency for sensor configuration and diagnostics.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| PCLK Range | 10–100 MHz; supports 12-bit mode up to 75 MHz or 10-bit mode up to 100 MHz - enables megapixel imaging at varying resolution/fps trade-offs |
| Parallel Interface | 12-bit LVCMOS outputs (ROUT[0:11]) + HSYNC/VSYNC; matches standard CMOS image sensor timing for direct FPGA/processor interfacing |
| Control Channel | I²C-compatible bidirectional bus (SCL/SDA) at 400 kHz; enables real-time sensor register access without interrupting video stream |
| Input Multiplexing | 2-channel differential input (RIN0±, RIN1±); hardware-selectable via SEL pin or software-controlled register for dual-camera architectures |
| ESD Robustness | ≥±25 kV air discharge (IEC 61000-4-2); qualified per AEC-Q100 Grade 2 (−40°C to +105°C) for under-hood automotive deployment |
| Power Supply | 1.8 V core (VDDPLL/VDDD/VDDCML0/1/VDDR/VDDSSCG); 1.8/2.8/3.3 V I/O (VDDIO1/2/3); enables mixed-voltage system integration |
| Package | 48-pin WQFN (RHS), 7.0 mm × 7.0 mm; thermally enhanced DAP ground pad with ≥16 vias for automotive thermal management |
Pinout & Package
DS90UB914QSQX/NOPB uses a 48-pin WQFN (RHS) package with 7.0 mm × 7.0 mm body size and exposed thermal pad (DAP) requiring ≥16 vias to ground plane. Pin functions are validated per TI SNLS420D Rev D datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ROUT[0:11] | LVCMOS parallel data output | 12-bit pixel data bus synchronized to PCLK; drives FPGA/ASIC video processors directly |
| HSYNC / VSYNC | Timing synchronization output | Active-high horizontal/vertical sync signals aligned to video frame boundaries for precise frame capture |
| PCLK | Pixel clock output | Reconstructed clock derived from embedded serial stream; edge-aligned to ROUT data for zero-skew sampling |
| RIN0± / RIN1± | Differential FPD-Link III input pair | AC-coupled inputs accepting serialized video from DS90UB913Q-Q1; support STP cabling up to 25 m |
| SCL / SDA | Bidirectional I²C control bus | Open-drain lines with external pullups; enable full-duplex sensor configuration and telemetry during video transmission |
| SEL | Multiplexer select input | LVCMOS input selecting RIN0± (SEL = L) or RIN1± (SEL = H); allows hardware-based dual-camera switching |
| LOCK | PLL lock status indicator | LVCMOS output high when PLL locked; used for link integrity monitoring and system fault detection |
| BISTEN / PASS | Built-in self-test control/status | BISTEN enables error-checking mode; PASS output asserts high on error-free payload reception - critical for safety validation |
| OEN / OSS_SEL | Output enable/sleep control | LVCMOS inputs controlling ROUT/PCLK drive state; allow dynamic power gating during idle periods |
| GPIO[0:3] | General-purpose I/O | Configurable as inputs for serializer GPO feedback or local register-driven outputs; support custom camera control logic |
Key Features
| Feature | Design Value |
|---|---|
| Embedded Clock + DC-Balanced Encoding | Eliminates separate clock routing and enables AC-coupled STP interconnects - reduces EMI and simplifies cable harness design |
| Adaptive Equalization | Automatically adjusts receiver gain to compensate for frequency-dependent cable loss - maintains signal integrity over 25 m STP |
| Programmable Spread Spectrum (SSCG) | Reduces peak radiated emissions from CML outputs - helps meet CISPR 25 Class 5 automotive EMC requirements |
| 2:1 Input Multiplexer | Hardware- and register-selectable dual-imager interface - enables cost-effective surround-view systems using single deserializer |
| AT-Speed BIST with PASS Output | Validates link integrity in real time without halting video; PASS pin provides deterministic pass/fail indication for ASIL-B diagnostics |
Applications
| Front-View Collision Mitigation | Rear-View Backup Camera |
|---|---|
Use Scenario: High-resolution forward-facing camera feeding video to ADAS ECU for pedestrian/object detection. IC Role / Device Role / Timing Role: Deserializes 12-bit 75-MHz video from CMOS imager over STP; reconstructs PCLK, HSYNC, VSYNC, and 12-bit pixel bus for FPGA processing. Use Value: Enables low-latency, noise-immune video transport in engine bay environments with validated −40°C to +105°C operation and >25 kV ESD protection. |
Use Scenario: Rear-mounted camera transmitting wide-angle video to infotainment display with minimal latency. IC Role / Device Role / Timing Role: Receives serialized video via RIN0±; outputs parallel ROUT[0:11], PCLK, and VSYNC to display controller with sub-µs jitter. Use Value: Supports 1080p@30fps over single STP cable; eliminates skew between clock/data paths and reduces connector pin count by >50% vs parallel interface. |
| Surround-View Parking Assistance | Driver Monitoring System (DMS) |
Use Scenario: Four-camera system fusing front/rear/left/right feeds into 360° stitched view using single ECU. IC Role / Device Role / Timing Role: Uses SEL pin to switch between RIN0± (front camera) and RIN1± (rear camera); shares one DS90UB914QSQX/NOPB across multiple sensors. Use Value: Reduces BOM cost and PCB area vs four discrete deserializers; maintains identical timing characteristics across all inputs for seamless stitching. |
Use Scenario: In-cabin IR camera capturing driver eye/gaze data for fatigue detection in autonomous driving modes. IC Role / Device Role / Timing Role: Deserializes low-latency 10-bit 100-MHz video; routes GPIO[2] to trigger IR LED strobes synchronized to PCLK edge. Use Value: Sub-microsecond control channel latency ensures precise illumination timing; LOCK output confirms continuous link health during critical monitoring intervals. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPD-Link III deserializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90UB914A-Q1 | Supports coaxial or STP media; higher PCLK range (25–100 MHz) but no 10–25 MHz low-frequency 12-bit mode | Targeted for longer-distance coax runs (>30 m) or higher-noise environments where STP shielding is insufficient | Select DS90UB914A-Q1 only if coax cabling is mandated or PCLK <25 MHz operation is not required |
| DS90UB954-Q1 | 4-lane FPD-Link IV deserializer; supports 16-bit payloads, 1.5 Gbps/lane, and integrated MIPI CSI-2 output | Designed for next-gen 4K+ cameras and domain controllers requiring native MIPI interface and higher bandwidth | Choose DS90UB954-Q1 for future-proofing beyond 12-bit/100-MHz limits or when MIPI CSI-2 output eliminates need for FPGA bridging |
Compared with DS90UB914A-Q1 and DS90UB954-Q1, DS90UB914QSQX/NOPB uniquely supports 10–25 MHz 12-bit operation for low-frame-rate thermal or NIR sensors, retains pin-compatibility with legacy DS90UB913Q-Q1 serializers, and offers lowest-cost entry into AEC-Q100-compliant FPD-Link III systems.
Availability
DS90UB914QSQX/NOPB is available at Aetrix Electronics and suitable for front-view collision mitigation, surround-view parking assistance, and driver monitoring systems requiring stable component supply, automotive qualification, and long-term production continuity.
Supply support for DS90UB914QSQX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and automotive ICs, with decades of leadership in high-reliability interface solutions.
The DS90UB914QSQX/NOPB belongs to TI's FPD-Link III automotive serializer/deserializer product line, designed specifically for robust, low-latency camera video transport in ADAS and automated driving ECUs.
FAQ
What is the maximum cable length supported by DS90UB914QSQX/NOPB?
DS90UB914QSQX/NOPB supports up to 25 meters of shielded twisted-pair (STP) cable, enabled by its adaptive equalizer that dynamically compensates for frequency-dependent insertion loss. Performance is validated at full 100-MHz PCLK with 10-bit payloads and 75-MHz with 12-bit payloads. Longer runs require DS90UB914A-Q1 with coax support.
Does DS90UB914QSQX/NOPB support both 10-bit and 12-bit pixel formats?
Yes, DS90UB914QSQX/NOPB supports configurable 10-bit mode (20–100 MHz PCLK) and 12-bit mode (10–75 MHz PCLK), selected via MODE pin resistor configuration per Table 8 in SNLS420D. The 12-bit low-frequency mode (10–50 MHz) is especially suited for thermal or NIR sensors requiring deeper bit depth at reduced frame rates.
How does the bidirectional control channel operate alongside video transmission?
The DS90UB914QSQX/NOPB bidirectional control channel uses the same differential pair as the forward video channel but operates in full-duplex via embedded-clock technology. It carries I²C traffic at up to 400 kHz independently of video blanking, enabling real-time sensor register reads/writes without interrupting the pixel stream or introducing latency.
Can DS90UB914QSQX/NOPB interface directly with an FPGA without level-shifting?
Yes, DS90UB914QSQX/NOPB supports 1.8-V, 2.8-V, and 3.3-V LVCMOS I/O on VDDIO pins, allowing direct connection to FPGA banks configured for matching voltage levels. ROUT[0:11], HSYNC, VSYNC, and PCLK are all LVCMOS outputs with ±4 mA drive strength and rail-to-rail swing - no external level shifters needed.
What is the function of the LOCK pin on DS90UB914QSQX/NOPB?
The LOCK pin on DS90UB914QSQX/NOPB is an LVCMOS output that asserts high when the internal PLL achieves lock to the incoming serial stream's embedded clock. It remains low during loss-of-signal or PLL unlock events, providing deterministic link-status feedback for system-level fault detection and ASIL-B diagnostic coverage.
DS90UB914QSQX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Deserializer
- Data Rate:
- 1.4Gbps
- Input Type:
- FPD-Link III, LVDS
- Output Type:
- LVCMOS
- Number of Inputs:
- 1
- Number of Outputs:
- 12
- Voltage - Supply:
- 1.71V ~ 1.89V, 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-WQFN (7x7)
DS90UB914QSQX/NOPB FAQ
1.How can I place an order for DS90UB914QSQX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90UB914QSQX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90UB914QSQX/NOPB reliable?
The price and inventory of DS90UB914QSQX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90UB914QSQX/NOPB is usually 5 days.
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Once your DS90UB914QSQX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90UB914QSQX/NOPB?
For technical support, including DS90UB914QSQX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90UB914QSQX/NOPB requirements.
6.How does Aetrix verify that DS90UB914QSQX/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90UB914QSQX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90UB914QSQX/NOPB meets industry standards.
7.What is the process for return or replacement of DS90UB914QSQX/NOPB?
All DS90UB914QSQX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90UB914QSQX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90UB914QSQX/NOPB part is unused and in its original packaging.
Return procedure for DS90UB914QSQX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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