My Inquiry
My Account
Texas Instruments DS90UB924TRHSTQ1
- Part No.:
- DS90UB924TRHSTQ1
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
DS90UB924TRHSTQ1.pdf
- Description:
- IC SERIALIZER 720P 48WQFN
- Quantity:
- Payment:
- Shipping:
Inventory:167
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90UB924TRHSTQ1 from Texas Instruments is an AEC-Q100 Grade 2 automotive-qualified FPD-Link III deserializer that converts a single-pair AC-coupled high-speed serial stream (5–96 MHz pixel clock) into four LVDS data lanes, one LVDS clock pair (OpenLDI), and up to four I2S audio channels. It supports RGB888 + HS/VS/DE timing and 720p digital video output for in-vehicle displays.
For engineers reviewing the DS90UB924TRHSTQ1 datasheet, DS90UB924TRHSTQ1 pinout, DS90UB924TRHSTQ1 application, or DS90UB924TRHSTQ1 equivalent, this page delivers verified technical context, validated pin functions, confirmed automotive-grade specifications, and real-world interface compatibility with DS90UB921-Q1 serializers and OpenLDI displays.
Technical Context
The DS90UB924TRHSTQ1 implements adaptive equalization on its FPD-Link III input (RIN±) to compensate for cable loss up to 100Q STP, enabling robust operation over long automotive harnesses. Its internal PLL locks to embedded clock data, generating precise TxCLKOUT± (5–96 MHz) and four synchronized TxOUT[3:0]± LVDS outputs compliant with OpenLDI timing standards.
It integrates bidirectional control via I²C (SCL/SDA), four configurable GPIOs (including shared I2S_DA/DB/DC/DD), and dedicated status pins (LOCK, PASS, INTB_IN). The device supports dual-voltage I/O (1.8 V or 3.3 V) and includes BIST, loop-through monitoring (CMLOUTP/N), and backward-compatible modes selected via MODE_SEL voltage divider.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Pixel Clock Range | 5 MHz to 96 MHz - supports 720p video with precise timing alignment across all four LVDS data lanes and clock pair. |
| Input Interface | Single-pair FPD-Link III (AC-coupled RIN±) - enables EMI-reduced, skew-free transmission over 100Ω STP cable. |
| Output Interface | OpenLDI LVDS: TxCLKOUT± + TxOUT[3:0]± - provides standard-compliant RGB888 video output with external 100Ω differential termination. |
| I²C Control | Standard/Fast-mode (100/400 kHz) with open-drain SCL/SDA - allows host processor configuration and status readback without additional level-shifting. |
| Audio Interface | Up to 4 I2S outputs (MCLK, I2S_WC, I2S_CLK, I2S_DA–DD) - delivers stereo or surround sound directly to audio DACs or processors. |
| Supply & I/O | Single 3.3-V VDD33 supply; 1.8-V or 3.3-V LVCMOS I/O (VDDIO) - simplifies power design while supporting legacy and low-power logic interfaces. |
| AEC-Q100 Grade | Grade 2 (−40°C to +105°C ambient) - qualified for instrument cluster, navigation, and touch display applications in passenger compartments. |
Pinout & Package
DS90UB924TRHSTQ1 is housed in a thermally enhanced 48-pin WQFN package (7.0 mm × 7.0 mm), with exposed thermal pad (DAP) requiring ≥9 vias to ground plane. Pin functions are validated per TI SNLS512 datasheet Rev. APRIL 2016.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RIN+, RIN− | FPD-Link III differential input | AC-coupled receiver inputs with adaptive equalization; require 0.1-µF series capacitors per TI layout guidelines. |
| TxCLKOUT+, TxCLKOUT− | LVDS clock output | OpenLDI-compliant clock pair; requires external 100-Ω differential termination for proper signal integrity. |
| TxOUT[3:0]+, TxOUT[3:0]− | LVDS data outputs | Four true/inverting LVDS data lanes carrying RGB888 + DE/HS/VS; each pair needs 100-Ω termination. |
| SCL, SDA | I²C bidirectional control bus | Open-drain interface with mandatory 4.7-kΩ pullups to VDD33; supports register access and status monitoring. |
| LOCK, PASS | Status outputs | LVCMOS signals indicating PLL lock state (LOCK) and BIST pass/fail (PASS); routed to test points or MCU GPIOs. |
| PDB | Power-down mode input | Active-high enable pin; must be driven or pulled up to VDD33; asserts tri-state outputs and shuts down PLL when low. |
Key Features
| Feature | Design Value |
|---|---|
| Adaptive cable equalization | Compensates for deterministic jitter and insertion loss on 100Ω STP cables up to 15 m, ensuring reliable link at 96 MHz. |
| Bidirectional I²C control channel | Enables full register read/write over same FPD-Link III physical layer used for video/audio, eliminating separate control wiring. |
| Integrated BIST engine | Generates and verifies PRBS patterns internally; PASS output indicates error-free serial link integrity without external test equipment. |
| Configurable OpenLDI mapping | MAPSEL pin selects MSB-first or LSB-first data routing across TxOUT[3:0]±, matching serializer output order (e.g., DS90UB921-Q1). |
| Four-channel I2S audio support | Delivers independent stereo streams (I2S_DA–DD) with MCLK, word clock, and bit clock - suitable for multi-zone car audio systems. |
| Backward compatibility modes | MODE_SEL voltage divider configures BKWD, REPEAT, I2S_B, or LCBL modes - enables interoperability with legacy FPD-Link II systems. |
Applications
| Automotive Touch Screen Display | Automotive Instrument Cluster |
|---|---|
|
Use Scenario: Central infotainment unit driving a 7-inch resistive/capacitive touchscreen with integrated graphics processor. IC Role / Device Role / Timing Role: Deserializes FPD-Link III video from host processor (e.g., DS90UB921-Q1) into OpenLDI format for display controller; provides I2S audio to touch feedback speaker. Use Value: Reduces interconnect count from >20 wires to 2 differential pairs (video + control), lowering EMI and harness weight while maintaining 720p timing accuracy. |
Use Scenario: Digital gauge cluster rendering speed, RPM, and ADAS alerts using high-brightness TFT LCD. IC Role / Device Role / Timing Role: Receives serialized video over long cable run (≥3 m) and reconstructs RGB888 + HS/VS/DE timing with sub-nanosecond skew control. Use Value: Adaptive equalization maintains signal integrity across temperature extremes (−40°C to +105°C), ensuring display reliability in all driving conditions. |
| Automotive Display for Navigation | Head-Up Display (HUD) Video Interface |
|
Use Scenario: Navigation system with map rendering, turn-by-turn guidance, and real-time traffic overlay on 10-inch display. IC Role / Device Role / Timing Role: Converts high-bandwidth video stream into OpenLDI-compatible parallel interface; supplies I2S audio for voice prompts. Use Value: Supports 96-MHz pixel clock for crisp 720p resolution and fast frame updates, minimizing motion blur during route recalculation. |
Use Scenario: Compact HUD module projecting navigation data onto windshield using DLP or LCoS microdisplay. IC Role / Device Role / Timing Role: Provides low-jitter TxCLKOUT± and tightly aligned TxOUT[3:0]± for precise pixel timing critical to optical projection fidelity. Use Value: <100 ps cycle-to-cycle jitter (tDCCJ) ensures stable image registration and eliminates horizontal tearing artifacts in projected imagery. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPD-Link III deserializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90UB926TRHSTQ1 | Same 48-pin WQFN package; adds eDP-compatible output (not OpenLDI); supports higher 1080p resolution. | Targeted at premium displays requiring eDP sink capability; not drop-in compatible for OpenLDI-only systems. | Select DS90UB926TRHSTQ1 only if migrating to eDP-based display architecture and redesigning PCB layout. |
| DS90UB940TRGZTQ1 | 10-bit color depth (vs. 24-bit), no I2S audio outputs, different pinout (64-pin ZQZ), and no BIST engine. | Designed for cost-sensitive clusters with basic graphics; lacks audio integration and diagnostic features. | Choose DS90UB940TRGZTQ1 for non-audio, lower-resolution instrument panels where BIST and I2S are unnecessary. |
Compared with DS90UB924TRHSTQ1, DS90UB926TRHSTQ1 extends resolution and interface flexibility at the cost of OpenLDI compatibility, while DS90UB940TRGZTQ1 reduces feature set and package size for simpler, lower-cost implementations - neither offers pin-to-pin replacement.
Availability
DS90UB924TRHSTQ1 is available at Aetrix Electronics and suitable for automotive instrument clusters, navigation displays, and touch screen interfaces requiring stable component supply, AEC-Q100 qualification, and long-term production continuity.
Supply support for DS90UB924TRHSTQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and automotive electronics, with decades of expertise in high-speed serial interface solutions.
The DS90UB924TRHSTQ1 belongs to TI's FPD-Link III automotive serializer/deserializer product line, engineered specifically for noise-immune, lightweight video distribution in vehicles - targeting display subsystems where EMI, weight, and reliability are critical.
FAQ
What is the maximum supported pixel clock frequency for DS90UB924TRHSTQ1?
The DS90UB924TRHSTQ1 supports pixel clock frequencies from 5 MHz to 96 MHz, enabling full 720p (1280×720 @ 60 Hz) video output with precise timing alignment. This range is specified under recommended operating conditions (TA = −40°C to +105°C, VDD33 = 3.3 V) and validated in TI SNLS512 datasheet Section 6.3.
Does DS90UB924TRHSTQ1 support I2S audio output, and how many channels are available?
Yes, DS90UB924TRHSTQ1 supports up to four I2S digital audio outputs (I2S_DA, I2S_DB, I2S_DC, I2S_DD) alongside MCLK, I2S_WC, and I2S_CLK - enabling stereo or multi-zone surround sound delivery. These outputs are LVCMOS and share pins with GPIO_REG[6:5] and GPIO[3:2], as defined in the pin function table (Section 5, SNLS512).
How does the adaptive equalization in DS90UB924TRHSTQ1 improve cable performance?
The DS90UB924TRHSTQ1 implements adaptive input equalization on its RIN± FPD-Link III receiver to compensate for high-frequency loss and deterministic jitter introduced by 100Ω STP cables. This enables reliable operation over extended lengths (up to 15 m) at 96 MHz without external equalizer ICs, reducing BOM cost and board space.
What is the role of the LOCK and PASS pins on DS90UB924TRHSTQ1?
LOCK is an LVCMOS output indicating PLL lock status (high = locked); PASS is an LVCMOS output signaling BIST result (high = error-free transmission). Both are used for system-level diagnostics: LOCK confirms stable video timing, while PASS validates serial link integrity - critical for functional safety monitoring in automotive displays.
Can DS90UB924TRHSTQ1 operate with both 1.8-V and 3.3-V LVCMOS I/O levels?
Yes, DS90UB924TRHSTQ1 supports dual-voltage LVCMOS I/O via the VDDIO pin, which accepts either 1.8 V (1.71–1.89 V) or 3.3 V (3.0–3.6 V) supplies. All GPIOs, I2S outputs, and control pins (SCL/SDA, MODE_SEL, etc.) auto-adapt to the selected VDDIO level, as detailed in Sections 6.5 and 6.6 of the SNLS512 datasheet.
DS90UB924TRHSTQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Deserializer
- Data Rate:
- -
- Input Type:
- LVCMOS
- Output Type:
- LVDS
- Number of Inputs:
- 4
- Number of Outputs:
- 4
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-WQFN (7x7)
DS90UB924TRHSTQ1 FAQ
1.How can I place an order for DS90UB924TRHSTQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90UB924TRHSTQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90UB924TRHSTQ1 reliable?
The price and inventory of DS90UB924TRHSTQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90UB924TRHSTQ1 is usually 5 days.
3.What payment methods are accepted for DS90UB924TRHSTQ1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90UB924TRHSTQ1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90UB924TRHSTQ1?
DS90UB924TRHSTQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90UB924TRHSTQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90UB924TRHSTQ1?
For technical support, including DS90UB924TRHSTQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90UB924TRHSTQ1 requirements.
6.How does Aetrix verify that DS90UB924TRHSTQ1 is sourced from the original manufacturer or authorized distributors?
All DS90UB924TRHSTQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90UB924TRHSTQ1 meets industry standards.
7.What is the process for return or replacement of DS90UB924TRHSTQ1?
All DS90UB924TRHSTQ1 units undergo pre-shipment inspection (PSI). If there is an issue with DS90UB924TRHSTQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90UB924TRHSTQ1 part is unused and in its original packaging.
Return procedure for DS90UB924TRHSTQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90UB924TRHSTQ1 Tags
-
SN65HVS880PWPR
Texas Instruments
-
SN65HVS882PWPR
Texas Instruments
-
FIN3386MTDX
onsemi
-
FIN3385MTDX
onsemi
-
SN65LV1023ARHBR
Texas Instruments
-
SN65LV1023ADBR
Texas Instruments
-
SN65LV1224BDBR
Texas Instruments
-
SN65LVDS93ADGGR
Texas Instruments
-
SN65LVDS93DGGR
Texas Instruments
-
TDES954RGZT
Texas Instruments
-
SN65LV1224BRHBT
Texas Instruments
-
DS90UB914QSQE/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
