Texas Instruments DS90UB934TRGZRQ1
- Part No.:
- DS90UB934TRGZRQ1
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
DS90UB934TRGZRQ1.pdf
- Description:
- IC DESERIALIZER 12 BIT 48VQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS90UB934TRGZRQ1 from Texas Instruments is an AEC-Q100 Grade 2 automotive FPD-Link III deserializer that converts high-speed serial video streams into 12-bit parallel CMOS outputs at up to 100 MHz, supporting 1MP/60fps and 2MP/30fps camera sensors in rear-view and surround-view systems. It features adaptive equalization for coaxial or STP cable compensation, Power-over-Coax (PoC) support, and ultra-low-latency bidirectional control channel with data protection.
For engineers reviewing the DS90UB934TRGZRQ1 datasheet, DS90UB934TRGZRQ1 pinout, DS90UB934TRGZRQ1 application, or DS90UB934TRGZRQ1 equivalent, key selection criteria include its 100-MHz 12-bit parallel output timing, AEC-Q100 Grade 2 qualification (–40°C to +105°C), dual-channel FPD-Link III input with SEL-controlled switching, PoC compatibility, and integrated BIST diagnostics.
Technical Context
The DS90UB934TRGZRQ1 implements a PLL-based clock recovery architecture synchronized to the incoming FPD-Link III forward channel, delivering pixel clock (PCLK), HSYNC, and VSYNC signals alongside 12-bit parallel data (ROUT0–ROUT11). Its adaptive equalizer dynamically compensates for cable loss across 50-Ω coaxial or 100-Ω STP media without firmware intervention.
It integrates dual independent FPD-Link III receivers (RIN0+/– and RIN1+/–), selectable via the SEL strap pin, and supports embedded bidirectional control channel communication over the same physical link using I²C-compatible protocol. The device provides four GPIOs (GPIO0–GPIO3/INTB), configurable as inputs or outputs, with programmable VIH/VIL thresholds and internal pulldowns.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| PCLK Frequency | Up to 100 MHz - enables real-time 1MP/60fps or 2MP/30fps image sensor interface with precise pixel timing. |
| Data Width | Configurable 10- or 12-bit parallel CMOS output - matches DS90UB913A/933 serializers and supports high-fidelity automotive imaging pipelines. |
| Operating Temp | –40°C to +105°C ambient - meets AEC-Q100 Grade 2 requirements for under-hood and exterior camera module placement. |
| ESD Rating | HBM ±2 kV, CDM C4, ISO 10605 ±8 kV contact - ensures robustness in automotive manufacturing and field environments. |
| Power Supply | VDD18 = 1.71–1.89 V; VDDIO = 1.71–1.89 V or 3.0–3.6 V - supports flexible system-level voltage domain partitioning. |
| Power Consumption | 685 mW typical at 100 MHz/12-bit mode - optimized for thermally constrained camera modules with active cooling constraints. |
| Cable Support | 50-Ω coaxial or 100-Ω STP - enables cost-effective single-cable video + power + control in ADAS camera links. |
Pinout & Package
DS90UB934TRGZRQ1 uses a 48-pin VQFN (RGZ) package with 7.00 mm × 7.00 mm body size and exposed thermal pad (DAP) for enhanced thermal dissipation in automotive camera modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ROUT0–ROUT11 | Parallel data output | 12-bit CMOS data bus (VDDIO-referenced); unused pins may be left unconnected. |
| PCLK, HSYNC, VSYNC | Timing signal outputs | Synchronous pixel clock and frame sync signals referenced to VDDIO; drive ISP or SoC video interface directly. |
| RIN0+/–, RIN1+/– | Differential FPD-Link III inputs | Dual-channel high-speed serial receiver with internal 100-Ω differential termination; supports AC-coupled coax or STP. |
| SEL | Input channel select | Strap pin selecting RIN0 (SEL = L) or RIN1 (SEL = H); internal 25-kΩ pulldown enables default single-channel operation. |
| I2C_SDA / I2C_SCL | Bidirectional control bus | Open-drain I²C interface (VI2C-referenced) for configuration and status readback; supports remote target addressing per TI documentation. |
| GPIO0–GPIO3/INTB | Configurable I/O | Four general-purpose pins; GPIO3 doubles as active-low open-drain interrupt (INTB) with programmable threshold and pullup to VI2C. |
| PDB | Power-down control | Inverted enable input (3.3-V tolerant); internal 50-kΩ pulldown ensures safe power-down on startup unless actively driven high. |
| LOCK, PASS | Link status indicators | LOCK = H confirms PLL lock and valid outputs; PASS = H indicates error-free forward channel transmission. |
Key Features
| Feature | Design Value |
|---|---|
| Adaptive equalization | Compensates for cable aging, temperature drift, and length variation in real time-no host MCU intervention required. |
| Power-over-Coax (PoC) | Enables simultaneous video, control, and DC power delivery over single coaxial cable-reducing harness weight and connector count. |
| Built-In Self-Test (BIST) | Verifies FPD-Link III link integrity and deserializer functionality during startup or diagnostic cycles-supports ASIL-B readiness. |
| Dual-input channel selection | Hardware-selectable RIN0 or RIN1 via SEL pin-enables redundant camera input or multi-sensor fusion without external multiplexers. |
| Ultra-low latency control channel | Sub-microsecond round-trip delay for register access and status polling-critical for real-time camera calibration and focus control. |
Applications
| Rear-View Camera (RVC) | Surround-View System (SVS) |
|---|---|
Use Scenario: High-resolution backup camera feeding video to central display or ADAS ECU via coaxial cable. IC Role / Device Role / Timing Role: Deserializes 1MP/60fps FPD-Link III stream into parallel CMOS for ISP processing; delivers PCLK, HSYNC, VSYNC with <1 ns jitter. Use Value: Enables low-latency, noise-immune video transport over long cable runs while supporting PoC to eliminate separate power wiring. | Use Scenario: Four-camera bird's-eye view system requiring synchronized image capture and low-jitter timing alignment. IC Role / Device Role / Timing Role: Receives and deserializes two independent FPD-Link III streams (via RIN0/RIN1 selection) with matched PCLK phase for frame synchronization. Use Value: Dual-input capability eliminates need for external muxes; adaptive equalization maintains timing integrity across varying cable lengths per camera. |
| Forward Vision Camera (FC) | Driver Monitoring System (DMS) |
Use Scenario: Front-facing ADAS camera operating in extreme ambient temperatures (–40°C to +105°C). IC Role / Device Role / Timing Role: Converts high-bandwidth video from global-shutter imager into parallel interface for SoC; provides LOCK and PASS status for functional safety monitoring. Use Value: AEC-Q100 Grade 2 qualification and integrated diagnostics support ASIL-B compliance in vision-based collision avoidance systems. | Use Scenario: In-cabin infrared camera capturing driver attention metrics with strict EMI and radiated emission limits. IC Role / Device Role / Timing Role: Deserializes low-light 2MP/30fps stream while maintaining low radiated emissions via spread-spectrum-capable clocking and optimized layout guidance. Use Value: Meets CISPR 25 Class 5 radiated emission requirements without added shielding-reducing BOM cost and module size. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPD-Link III deserializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90UB914TRGZRQ1 | Lower max PCLK (85 MHz), no dual-input channel support, no PoC, older equalization algorithm. | Supports only 1MP/30fps or lower resolution; lacks SVS redundancy and PoC simplification. | Select when cost sensitivity outweighs bandwidth and feature requirements; not suitable for 1MP/60fps or PoC designs. |
| DS90UB954TRGZRQ1 | Higher bandwidth (1.92 Gbps), supports 4MP/30fps, adds MIPI CSI-2 output, enhanced BIST and diagnostics. | Targets next-gen ADAS with higher resolution and MIPI-native SoCs; requires updated PCB layout and firmware. | Choose for future-proofing or migration to MIPI-based vision processors; over-spec for current 1MP/60fps RVC/SVS needs. |
Compared with DS90UB914TRGZRQ1, DS90UB934TRGZRQ1 delivers 18% higher pixel clock headroom and dual-input flexibility critical for SVS fault tolerance; versus DS90UB954TRGZRQ1, it offers proven maturity, lower system cost, and simpler integration for established 12-bit CMOS ISP interfaces.
Availability
DS90UB934TRGZRQ1 is available at Aetrix Electronics and suitable for automotive rear-view cameras, surround-view systems, and forward-vision ADAS modules requiring stable component supply, AEC-Q100-compliant logistics, and long-term production continuity.
Supply support for DS90UB934TRGZRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a U.S.-based semiconductor company specializing in analog, embedded processing, and automotive ICs, with decades of leadership in high-speed interface solutions.
The DS90UB934TRGZRQ1 belongs to TI's FPD-Link III automotive serializer/deserializer product line, designed specifically to meet the bandwidth, reliability, and functional safety demands of ADAS camera links-including RVC, SVS, FC, and DMS.
FAQ
What is the maximum supported pixel clock frequency for DS90UB934TRGZRQ1?
The DS90UB934TRGZRQ1 supports a maximum PCLK frequency of 100 MHz in 12-bit mode, enabling real-time transmission of 1MP/60fps or 2MP/30fps image data from automotive camera sensors. This specification is validated across the full –40°C to +105°C operating range and is documented in Section 4.3 of the DS90UB934TRGZRQ1 datasheet.
Does DS90UB934TRGZRQ1 support Power-over-Coax (PoC)?
Yes, DS90UB934TRGZRQ1 explicitly supports Power-over-Coax operation as stated in its official features list and Section 6.2 of the datasheet. It enables bidirectional DC power delivery over the same coaxial cable used for FPD-Link III video and control data, reducing wiring complexity in automotive camera modules.
How does the adaptive equalization in DS90UB934TRGZRQ1 function without host intervention?
The DS90UB934TRGZRQ1 implements fully autonomous adaptive equalization that continuously monitors incoming signal integrity and adjusts receiver gain and filtering in real time. No register writes or MCU involvement are required-this behavior is hardware-defined and operates across all supported cable types (50-Ω coaxial or 100-Ω STP) and lengths.
Can DS90UB934TRGZRQ1 interface with both 1.8-V and 3.3-V logic systems?
Yes, DS90UB934TRGZRQ1 supports dual VDDIO ranges: 1.71–1.89 V and 3.0–3.6 V. Its LVCMOS I/Os (ROUT[11:0], PCLK, GPIOs, etc.) are fully compatible with either rail, with corresponding VOH/VOL and VIH/VIL thresholds specified in Sections 4.5.1 and 4.5.2 of the DS90UB934TRGZRQ1 datasheet.
What is the purpose of the SEL pin on DS90UB934TRGZRQ1?
The SEL pin on DS90UB934TRGZRQ1 selects between two independent FPD-Link III input channels: SEL = L activates RIN0+/–, and SEL = H activates RIN1+/–. This hardware-strapped feature enables dual-camera input routing without external multiplexers-critical for redundancy in surround-view systems and multi-sensor ADAS architectures.
Is DS90UB934TRGZRQ1 qualified for automotive safety standards beyond AEC-Q100?
DS90UB934TRGZRQ1 is AEC-Q100 Grade 2 qualified (–40°C to +105°C ambient), with documented HBM ±2 kV and CDM C4 ESD ratings. While it is not ISO 26262-certified as a standalone component, its LOCK and PASS status outputs, BIST capability, and diagnostic registers support integration into ASIL-B compliant systems per functional safety development guidelines.
DS90UB934TRGZRQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Deserializer
- Data Rate:
- 1.87Gbps
- Input Type:
- FPD-Link III, LVDS
- Output Type:
- LVCMOS
- Number of Inputs:
- 1
- Number of Outputs:
- 12
- Voltage - Supply:
- 1.71V ~ 1.89V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-VQFN (7x7)
DS90UB934TRGZRQ1 FAQ
1.How can I place an order for DS90UB934TRGZRQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90UB934TRGZRQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90UB934TRGZRQ1 reliable?
The price and inventory of DS90UB934TRGZRQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90UB934TRGZRQ1 is usually 5 days.
3.What payment methods are accepted for DS90UB934TRGZRQ1?
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4.How is shipping managed for DS90UB934TRGZRQ1?
DS90UB934TRGZRQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90UB934TRGZRQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90UB934TRGZRQ1?
For technical support, including DS90UB934TRGZRQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90UB934TRGZRQ1 requirements.
6.How does Aetrix verify that DS90UB934TRGZRQ1 is sourced from the original manufacturer or authorized distributors?
All DS90UB934TRGZRQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90UB934TRGZRQ1 meets industry standards.
7.What is the process for return or replacement of DS90UB934TRGZRQ1?
All DS90UB934TRGZRQ1 units undergo pre-shipment inspection (PSI). If there is an issue with DS90UB934TRGZRQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90UB934TRGZRQ1 part is unused and in its original packaging.
Return procedure for DS90UB934TRGZRQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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