Texas Instruments DS90UB940TNKDTQ1
- Part No.:
- DS90UB940TNKDTQ1
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 64-WFQFN Exposed Pad
- Datasheet:
-
DS90UB940TNKDTQ1.pdf
- Description:
- IC SER/DESER 25-170 MHZ FPD 64WQ
- Quantity:
- Payment:

- Shipping:

Inventory:250
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Product details
Overview
DS90UB940TNKDTQ1 from Texas Instruments is an AEC-Q100 Grade 2 automotive FPD-Link III deserializer that converts 1- or 2-lane FPD-Link III serial streams into MIPI CSI-2 output, supporting up to 1080p60/170 MHz pixel clock with 24-bit color depth. It features adaptive equalization (–15.3 dB @ 1.7 GHz), dual CSI-2 ports (2- or 4-lane selectable per port), and integrated I²C/SPI control over the same differential link. Used in central infotainment displays and digital instrument clusters.
For engineers reviewing the DS90UB940TNKDTQ1 datasheet, DS90UB940TNKDTQ1 pinout, DS90UB940TNKDTQ1 application, or DS90UB940TNKDTQ1 equivalent, key selection criteria include FPD-Link III deskew capability, CSI-2 lane configuration flexibility, AEC-Q100 Grade 2 qualification, adaptive equalization range, and support for dual-link operation with independent virtual channel assignment.
Technical Context
The DS90UB940TNKDTQ1 implements a fully autonomous FPD-Link III receiver with automatic channel detection and hardware-accelerated deskew-no training patterns required. Its dual-port MIPI D-PHY transmitter supports independent lane count (2 or 4 lanes per port) and programmable virtual channel IDs for multi-sensor routing.
It integrates adaptive receive equalization compensating for cable aging and temperature drift, plus dual-mode I²C (up to 1 Mbps Fast Mode Plus) and SPI (up to 3.3 Mbps) interfaces for configuration. The device supports 7.1-channel I²S audio with master/slave mode selection and configurable MCLK/word clock/data outputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Interface | 1- or 2-lane FPD-Link III with automatic deskew and no training pattern requirement |
| Output Interface | Dual MIPI CSI-2 ports, each configurable for 2- or 4-lane operation at up to 1.3 Gbps/lane |
| Max Pixel Clock | 170 MHz - enables WUXGA (1920×1200) and 1080p60 video with 24-bit color |
| Equalization Range | –15.3 dB insertion loss compensation at 1.7 GHz, with auto temperature/cable aging adaptation |
| Operating Temp | –40°C to +105°C ambient - AEC-Q100 Grade 2 qualified for automotive cabin environments |
| I²C Speed | Up to 1 Mbps Fast Mode Plus - supports high-speed register access without bus contention |
| SPI Speed | Up to 3.3 Mbps - enables rapid configuration of CSI-2 timing, VCID, and lane mapping |
Pinout & Package
DS90UB940TNKDTQ1 is housed in a 64-pin WQFN package (9.0 mm × 9.0 mm) with wettable flanks, optimized for automotive PCB assembly and thermal dissipation in constrained display module layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CSI0_CLK+/–, CSI0_D0–3+/– | MIPI CSI-2 Port 0 differential outputs | Primary camera/video interface; supports 2- or 4-lane configuration for sensor data routing |
| CSI1_CLK+/–, CSI1_D0–3+/– | MIPI CSI-2 Port 1 differential outputs | Secondary independent CSI-2 port for dual-sensor or redundancy applications |
| RIN0+/–, RIN1+/– | FPD-Link III differential inputs | Accepts serialized video/control from DS90UH949-Q1 or compatible serializers over STP/coax |
| I2C_SDA/SCL | Open-drain I²C bidirectional interface | Configures device registers and reads status; supports Fast Mode Plus (1 Mbps) |
| PDB | Inverted power-down control input | Active-HIGH enable; internal 3 µA pulldown ensures safe power-down on startup until MCU asserts |
| LOCK | PLL lock status indicator | Open-drain output signals stable FPD-Link III clock recovery - critical for system boot validation |
Key Features
| Feature | Design Value |
|---|---|
| Automatic FPD-Link III deskew | Hardware-accelerated alignment of multi-lane skew without firmware intervention or training sequences |
| Dual independent CSI-2 ports | Enables simultaneous connection to two image signal processors or redundant display paths |
| Adaptive equalization | Real-time compensation for cable degradation and temperature drift - eliminates manual tuning |
| Programmable virtual channel ID | Allows multiplexing of multiple sensors onto shared CSI-2 infrastructure with hardware-level routing |
| 7.1-channel I²S audio support | Offloads audio transport from main processor - supports multi-zone infotainment with low latency |
Applications
| Central Infotainment Display | Rear Seat Entertainment |
|---|---|
Use Scenario: High-resolution video feed from front-facing camera or media source routed to 10.25″ LCD cluster display. IC Role / Device Role / Timing Role: Deserializes FPD-Link III video from head unit or graphics processor and delivers synchronized CSI-2 stream to display controller. Use Value: Enables single-cable video+control transmission over coax/STP, reducing EMI and harness weight while maintaining 1080p60 timing integrity. |
Use Scenario: Dual-screen rear entertainment system receiving independent video feeds from two sources. IC Role / Device Role / Timing Role: Provides two independent CSI-2 output ports (CSI0 and CSI1), each configurable for 2- or 4-lane operation. Use Value: Eliminates need for two separate deserializers - reduces BOM cost and PCB area while enabling synchronized dual-display playback. |
| Digital Instrument Cluster | ADAS Camera Aggregation |
Use Scenario: Real-time rendering of vehicle speed, ADAS alerts, and navigation overlays on TFT cluster with <10 ms latency. IC Role / Device Role / Timing Role: Receives time-critical video from surround-view processor via FPD-Link III and outputs low-jitter CSI-2 to GPU. Use Value: LOCK pin provides hardware-validated PLL lock confirmation before display initialization - ensures deterministic boot timing. |
Use Scenario: Aggregating video from four surround-view cameras into a single processing pipeline. IC Role / Device Role / Timing Role: Assigns unique virtual channel IDs per camera stream; routes all to one CSI-2 port with lane multiplexing. Use Value: Virtual channel tagging enables software-level demux without additional deserializer ICs or FPGA logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPD-Link III deserialization applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90UB947QSQ | Single-port CSI-2 output (4-lane max); no dual-port capability; lower pin count (48-pin VQFN) | Targeted at cost-sensitive single-display systems without multi-sensor aggregation needs | Select when only one CSI-2 sink is required and board space is constrained |
| DS90UB954TRGCRQ1 | Supports 4-lane FPD-Link III input; higher bandwidth (216 MHz pixel clock); includes embedded HDCP engine | Required for premium infotainment with content protection and >1080p resolution | Select when HDCP compliance or WQXGA resolution support is mandatory |
Compared with DS90UB940TNKDTQ1, DS90UB947QSQ reduces system complexity for single-display use cases but sacrifices dual-port flexibility, while DS90UB954TRGCRQ1 adds HDCP and higher bandwidth at the cost of increased power and layout complexity - making DS90UB940TNKDTQ1 the optimal balance for mainstream AEC-Q100 dual-display automotive designs.
Availability
DS90UB940TNKDTQ1 is available at Aetrix Electronics and suitable for automotive infotainment displays, digital instrument clusters, and rear seat entertainment systems requiring stable component supply across extended product lifecycles.
Supply support for DS90UB940TNKDTQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with deep expertise in automotive-grade interface solutions.
The DS90UB940TNKDTQ1 belongs to TI's FPD-Link III automotive serializer/deserializer family, designed specifically to replace bulky LVDS interconnects with high-reliability, EMI-robust, single-cable video+control links for next-generation vehicle displays.
FAQ
What is the maximum supported resolution and frame rate for DS90UB940TNKDTQ1?
The DS90UB940TNKDTQ1 supports up to 1080p60 resolution with 24-bit color depth, enabled by its 170 MHz maximum pixel clock capability. This allows full HD video transmission for central displays and digital instrument clusters. The device also supports WUXGA (1920×1200) at lower frame rates. Resolution and timing are configured via register settings and depend on the connected FPD-Link III serializer's capabilities. DS90UB940TNKDTQ1 does not perform scaling or format conversion - it transparently forwards validated video data.
Does DS90UB940TNKDTQ1 require external training patterns for FPD-Link III deskew?
No, DS90UB940TNKDTQ1 performs automatic hardware-based deskew without requiring training patterns. It detects FPD-Link III channel presence and applies real-time alignment to compensate for inter-pair skew caused by PCB routing mismatches, cable length differences, or connector imbalances. This eliminates firmware overhead and ensures robust lock acquisition across temperature and aging conditions. DS90UB940TNKDTQ1 achieves this using embedded phase detectors and adaptive delay lines within its receiver architecture.
How many MIPI CSI-2 lanes can DS90UB940TNKDTQ1 drive simultaneously?
DS90UB940TNKDTQ1 supports two independent MIPI CSI-2 ports (CSI0 and CSI1), each configurable for either 2-lane or 4-lane operation - for a total of up to 8 active CSI-2 data lanes. Lane count per port is set via MODE_SEL pins and register configuration. Each lane operates at up to 1.3 Gbps, enabling aggregate bandwidth sufficient for dual 1080p streams. DS90UB940TNKDTQ1 does not share lanes between ports; each port maintains full electrical and protocol independence.
What power supply rails does DS90UB940TNKDTQ1 require?
DS90UB940TNKDTQ1 requires three primary supply rails: VDD12 (1.2 V for core logic), VDD33 (3.3 V for I/O and analog circuits), and VDDIO (configurable 1.8 V or 3.3 V for CSI-2 and I²C/SPI interfaces). The device includes dedicated power domains for CSI-2 transmitters (VDD12_CSI1), FPD-Link III receivers (VDDL12_0/1), and GPIOs. Power sequencing must follow TI's recommended order: VDD12 first, then VDD33, then VDDIO - with PDB held low until all supplies stabilize. DS90UB940TNKDTQ1 monitors supply integrity internally and asserts LOCK only after valid regulation.
Is DS90UB940TNKDTQ1 pin-compatible with other devices in the DS90UB9xx-Q1 family?
No, DS90UB940TNKDTQ1 is not pin-compatible with other members of the DS90UB9xx-Q1 family. Its 64-pin WQFN package and specific pin assignments - including dual CSI-2 port outputs, dual FPD-Link III inputs, and dedicated I²S routing - differ from variants like DS90UB947QSQ (48-pin) or DS90UB954TRGCRQ1 (64-pin but different pinout). Migration requires PCB redesign. DS90UB940TNKDTQ1's pin functions are documented in Section 5 of the SNLS479B datasheet, and unused pins must be left as No Connect per TI's guidance - not tied high/low unless explicitly specified.
DS90UB940TNKDTQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Deserializer
- Data Rate:
- 3.36Gbps
- Input Type:
- FPD-Link III, LVDS
- Output Type:
- CSI-2, MIPI
- Number of Inputs:
- 2
- Number of Outputs:
- 4
- Voltage - Supply:
- 1.71V ~ 1.89V, 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-WQFN (9x9)
DS90UB940TNKDTQ1 FAQ
1.How can I place an order for DS90UB940TNKDTQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90UB940TNKDTQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90UB940TNKDTQ1 reliable?
The price and inventory of DS90UB940TNKDTQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90UB940TNKDTQ1 is usually 5 days.
3.What payment methods are accepted for DS90UB940TNKDTQ1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90UB940TNKDTQ1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90UB940TNKDTQ1?
DS90UB940TNKDTQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90UB940TNKDTQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90UB940TNKDTQ1?
For technical support, including DS90UB940TNKDTQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90UB940TNKDTQ1 requirements.
6.How does Aetrix verify that DS90UB940TNKDTQ1 is sourced from the original manufacturer or authorized distributors?
All DS90UB940TNKDTQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90UB940TNKDTQ1 meets industry standards.
7.What is the process for return or replacement of DS90UB940TNKDTQ1?
All DS90UB940TNKDTQ1 units undergo pre-shipment inspection (PSI). If there is an issue with DS90UB940TNKDTQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90UB940TNKDTQ1 part is unused and in its original packaging.
Return procedure for DS90UB940TNKDTQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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