My Inquiry
My Account
Texas Instruments DS90UB941ASRTDRQ1
- Part No.:
- DS90UB941ASRTDRQ1
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 64-VFQFN Exposed Pad
- Datasheet:
-
DS90UB941ASRTDRQ1.pdf
- Description:
- INTERFACE IC MISC
- Quantity:
- Payment:
- Shipping:
Inventory:1,816
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90UB941ASRTDRQ1 from Texas Instruments is an AEC-Q100 Grade 2 automotive-qualified dual MIPI DSI-to-FPD-Link III bridge serializer supporting up to 210 MHz pixel clock for 2K (2880×1080) at 30 Hz, WUXGA, and 1080p60 with 24-bit color depth. It features dual 4-lane DSI inputs (up to 1.5 Gbps/lane), single/dual FPD-Link III outputs, symmetric/asymmetric video splitting, and functional safety documentation for ISO 26262 system design. It enables high-bandwidth video consolidation over coaxial or STP cables in infotainment head units.
For engineers reviewing the DS90UB941ASRTDRQ1 datasheet, DS90UB941ASRTDRQ1 pinout, DS90UB941ASRTDRQ1 application, or DS90UB941ASRTDRQ1 equivalent, this page delivers verified technical context, validated pin functions, real-world automotive use cases, confirmed alternatives, and supply-ready procurement support - all grounded in TI's production-grade SNLS640C specification.
Technical Context
The DS90UB941ASRTDRQ1 implements a dual-input DSI receiver with two independent 4-lane ports (DSI0/DSI1), each supporting MIPI D-PHY HS mode up to 1.5 Gbps per lane and 750 MHz DSI clock frequency. Its serializer core maps DSI video packets-including virtual channel and ECC/CRC-protected payloads-into FPD-Link III forward channels with full-duplex I²C and up to eight I²S audio lanes embedded in the same serial stream.
It supports three operational modes: single-link (≤105 MHz pixel clock), dual-link (≤210 MHz), and splitter modes (symmetric 2:2 or asymmetric cropping). Dual-link operation activates SPI interface pins (MOSI/MISO/SPLK/SS) and requires separate REFCLK0/REFCLK1 inputs with ±100 ppm stability; loop filter pins (LFDSI, LFT) mandate 10 nF decoupling to ground.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Pixel Clock Support | Up to 210 MHz for dual-link FPD-Link III output - enables 2K (2880×1080) @30Hz, 1080p60, or WUXGA resolution with 24-bit color |
| DSI Input Capability | Dual 4-lane ports (DSI0 + DSI1), each up to 1.5 Gbps/lane - supports MIPI D-PHY HS mode and virtual channel tagging |
| FPD-Link III Output | Single or dual differential links; dual-link achieves 3.675 Gbps line rate - transmits video, I²C control, and up to 8 I²S audio channels over one cable |
| Operating Temperature | −40°C to +105°C ambient - qualified per AEC-Q100 Grade 2 for under-hood and dashboard-mounted infotainment systems |
| Power Supply | VDD11 = 1.1 V ±5%, VDD18 = 1.8 V ±5%, VDDIO = 1.8 V or 3.3 V - requires dedicated 0.1 µF decoupling per supply pin group |
| Total Power Consumption | 800 mW typical in dual-link mode with 4-lane DSI input and checkerboard pattern - optimized for thermal management in compact VQFN-64 packages |
| ESD Robustness | ±8 kV HBM on FPD-Link III outputs (DOUT0±/DOUT1±); ±2.5 kV HBM on all other pins - meets automotive ESD immunity requirements |
Pinout & Package
DS90UB941ASRTDRQ1 uses a 64-pin VQFN package (9.0 mm × 9.0 mm body size) with exposed thermal pad (DAP) centered on the bottom side for PCB-level heat dissipation. Pin assignment follows TI's RTD package layout with strict separation of analog (LFDSI, LFT), high-speed serial (DSI, FPD-Link), and digital control (I²C, GPIO, REFCLK) domains.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DSI0_D0P–DSI0_D3N, DSI0_CLKP/CLKN | DSI Port 0 differential data/clock inputs | Accepts up to 4-lane MIPI DSI HS signals; unused lanes may be grounded or left NC |
| DSI1_D0P–DSI1_D3N, DSI1_CLKP/CLKN | DSI Port 1 differential data/clock inputs | Enables dual-source video ingestion (e.g., processor + FPGA); independent lane enable/disable via registers |
| DOUT0+, DOUT0−, DOUT1+, DOUT1− | FPD-Link III TX differential outputs | Drive coaxial or STP cables; AC-coupled per TI Table 9-1; support embedded I²C and I²S |
| REFCLK0, REFCLK1 | External reference clock inputs | Required for dual-link or splitter modes; 25 kΩ internal pulldown; accept 25–210 MHz low-jitter clocks |
| I2C_SDA, I2C_SCL | Open-drain I²C interface | Configures device registers and monitors status; 1.8 V/3.3 V compatible with 2.2–4.7 kΩ pullups |
| PDB | Inverted power-down control | Active-high enable; internal 50 kΩ pulldown ensures safe power-down until supplies stabilize |
| INTB | Active-low interrupt output | Signals error conditions (e.g., DSI sync loss, CRC failure); open-drain with 4.7 kΩ pullup to VDDIO |
Key Features
| Feature | Design Value |
|---|---|
| Symmetric & asymmetric video splitting | Enables simultaneous driving of two displays (e.g., instrument cluster + center stack) with independent resolution scaling and cropping - no external FPGA required |
| Functional Safety documentation | Provides failure modes, diagnostic coverage analysis, and safety mechanism guidance aligned with ISO 26262 ASIL B system integration |
| Embedded audio transport | Carries up to eight I²S audio channels alongside video over same FPD-Link III link - eliminates separate audio interconnects |
| EMI-reduced signaling | Uses LVDS-based FPD-Link III with data scrambling and randomization - meets CISPR 25 Class 5 radiated emissions limits in automotive cabins |
| Backward-compatible single-link mode | Supports WXGA/720p over one differential pair - simplifies migration from legacy designs without redesigning cabling |
Applications
| IVI Head Unit Video Aggregation | Digital Instrument Cluster Driving |
|---|---|
Use Scenario: Consolidating video streams from SoC and ADAS processor into a single high-resolution display using coaxial cabling. IC Role / Device Role / Timing Role: Dual DSI-to-FPD-Link III serializer performing real-time video packet mapping, ECC insertion, and dual-link serialization. Use Value: Reduces interconnect count by 50% versus discrete DSI-to-LVDS solutions while maintaining 210 MHz pixel clock timing integrity. |
Use Scenario: Driving a 12.3-inch digital gauge cluster with split-screen rendering (speedometer + navigation preview) from two independent DSI sources. IC Role / Device Role / Timing Role: Asymmetric video splitter generating two independent FPD-Link III streams with different resolutions and refresh rates. Use Value: Eliminates need for secondary graphics processor; enables pixel-accurate cropping and VC-ID routing without frame buffer latency. |
| Rear Seat Entertainment Distribution | Central Display Multi-Source Switching |
Use Scenario: Transmitting HD video from media player and camera feed simultaneously to dual rear-seat displays over shielded twisted-pair. IC Role / Device Role / Timing Role: Dual-link serializer with embedded I²C and I²S transport enabling bidirectional control and synchronized audio playback. Use Value: Delivers full-duplex control and eight-channel audio over same physical link - cuts wiring harness weight by >300 g. |
Use Scenario: Switching between infotainment UI and vehicle settings UI on a shared 10.25-inch center display using two DSI video pipelines. IC Role / Device Role / Timing Role: High-speed DSI multiplexer with seamless source arbitration and glitch-free transitions via register-controlled mode switching. Use Value: Achieves sub-frame (<16 ms) switching latency with zero visible artifacts - critical for driver attention retention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar DSI-to-FPD-Link III bridge applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90UB949TRGCRQ1 | Single DSI input (4-lane), dual FPD-Link III outputs; no video splitting; supports up to 210 MHz pixel clock | Lacks symmetric/asymmetric splitting and dual DSI ingestion - suitable only for single-source, dual-display systems | Select when system uses one video source and requires simpler configuration; lower pin count and BOM cost |
| DS90UB954TRGCRQ1 | Quad DSI input (2×4-lane), dual FPD-Link III outputs; adds MIPI CSI-2 receiver capability; same 210 MHz max pixel clock | Supports hybrid DSI+CSI-2 video aggregation (e.g., display + surround-view camera); larger 72-pin VQFN package | Choose when integrating camera feeds alongside display video; requires additional CSI-2 layout and clocking resources |
Compared with DS90UB949TRGCRQ1 and DS90UB954TRGCRQ1, the DS90UB941ASRTDRQ1 uniquely delivers dual DSI ingestion plus hardware-accelerated video splitting in a 64-pin VQFN - making it the only option for cost-sensitive, space-constrained automotive head units requiring two independent video sources and split-display output without external logic.
Availability
DS90UB941ASRTDRQ1 is available at Aetrix Electronics and suitable for automotive infotainment head units, digital instrument clusters, central information displays, and rear seat entertainment systems requiring stable component supply across extended product lifecycles.
Supply support for DS90UB941ASRTDRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and automotive ICs, with decades of leadership in high-speed serial interface technology and AEC-Q100 qualification expertise.
The DS90UB941ASRTDRQ1 belongs to TI's FPD-Link III automotive serializer family, designed specifically to replace bulky LVDS and parallel RGB interfaces in next-generation automotive displays while meeting stringent EMI, safety, and thermal requirements.
FAQ
What is the maximum supported DSI data rate per lane for DS90UB941ASRTDRQ1?
The DS90UB941ASRTDRQ1 supports up to 1.5 Gbps per DSI lane across both DSI0 and DSI1 ports, corresponding to a maximum DSI clock frequency of 750 MHz in high-speed mode. This enables full 24-bit color transmission for 2K and 1080p60 resolutions. The device also supports backward-compatible modes down to 150 Mbps per lane for legacy WXGA/720p systems.
Does DS90UB941ASRTDRQ1 require external loop filter components?
Yes, DS90UB941ASRTDRQ1 requires two external 10 nF capacitors: one between LFDSI and ground for the DSI PLL loop filter, and another between LFT and ground for the FPD-Link III PLL loop filter. These are mandatory for stable clock recovery and must be placed within 3 mm of their respective pins per TI layout guidelines in SNLS640C Section 11.
Can DS90UB941ASRTDRQ1 operate in single-link mode without REFCLK inputs?
Yes, DS90UB941ASRTDRQ1 operates in single-link mode using only the internal DSI clock as reference - REFCLK0 and REFCLK1 are not required. These pins are only mandatory in dual-link or splitter modes (symmetric/asymmetric), where independent pixel clock generation per output link is needed.
How does DS90UB941ASRTDRQ1 handle ECC and CRC protection?
DS90UB941ASRTDRQ1 generates and validates ECC for DSI payload data and CRC for DSI video packet headers. When enabled via BRIDGE_CTL register (0x4Fh), it inserts ECC bits into transmitted FPD-Link III streams and checks incoming DSI packets for bit errors, reporting failures via INTB assertion and DSI_ERR_COUNT register - critical for ASIL-B functional safety compliance.
What is the thermal performance of DS90UB941ASRTDRQ1 in its VQFN-64 package?
DS90UB941ASRTDRQ1 in the 9.0 mm × 9.0 mm VQFN package has a junction-to-board thermal resistance (RθJB) of 7.9°C/W and junction-to-ambient (RθJA) of 24.2°C/W. With proper PCB copper pour under the DAP thermal pad and ≥4 thermal vias, it sustains 800 mW power dissipation at 105°C ambient - validated per TI's SNLS640C Section 7.4 thermal metrics.
DS90UB941ASRTDRQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Serializer
- Data Rate:
- 1.5Gbps
- Input Type:
- MIPI DSI
- Output Type:
- FPD-Link III, LVDS
- Number of Inputs:
- 4
- Number of Outputs:
- 2
- Voltage - Supply:
- 1.045V ~ 1.155V, 1.71V ~ 1.89V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-VQFN (9x9)
DS90UB941ASRTDRQ1 FAQ
1.How can I place an order for DS90UB941ASRTDRQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90UB941ASRTDRQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90UB941ASRTDRQ1 reliable?
The price and inventory of DS90UB941ASRTDRQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90UB941ASRTDRQ1 is usually 5 days.
3.What payment methods are accepted for DS90UB941ASRTDRQ1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90UB941ASRTDRQ1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90UB941ASRTDRQ1?
DS90UB941ASRTDRQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90UB941ASRTDRQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90UB941ASRTDRQ1?
For technical support, including DS90UB941ASRTDRQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90UB941ASRTDRQ1 requirements.
6.How does Aetrix verify that DS90UB941ASRTDRQ1 is sourced from the original manufacturer or authorized distributors?
All DS90UB941ASRTDRQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90UB941ASRTDRQ1 meets industry standards.
7.What is the process for return or replacement of DS90UB941ASRTDRQ1?
All DS90UB941ASRTDRQ1 units undergo pre-shipment inspection (PSI). If there is an issue with DS90UB941ASRTDRQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90UB941ASRTDRQ1 part is unused and in its original packaging.
Return procedure for DS90UB941ASRTDRQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90UB941ASRTDRQ1 Tags
-
SN65HVS880PWPR
Texas Instruments
-
SN65HVS882PWPR
Texas Instruments
-
FIN3386MTDX
onsemi
-
FIN3385MTDX
onsemi
-
SN65LV1023ARHBR
Texas Instruments
-
SN65LV1023ADBR
Texas Instruments
-
SN65LV1224BDBR
Texas Instruments
-
SN65LVDS93ADGGR
Texas Instruments
-
SN65LVDS93DGGR
Texas Instruments
-
TDES954RGZT
Texas Instruments
-
SN65LV1224BRHBT
Texas Instruments
-
DS90UB914QSQE/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
