My Inquiry
My Account
Texas Instruments DS90UB962WRTDRQ1
- Part No.:
- DS90UB962WRTDRQ1
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 64-VFQFN Exposed Pad
- Datasheet:
-
DS90UB962WRTDRQ1.pdf
- Description:
- INTERFACE IC MISC
- Quantity:
- Payment:
- Shipping:
Inventory:2,000
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90UB962WRTDRQ1 from Texas Instruments is an AEC-Q100 Grade 2 automotive quad FPD-Link III deserializer hub that aggregates up to four 3-Gbps video streams into a single MIPI CSI-2 output. It supports 1-MP sensors at 30/60 Hz, delivers precise multi-camera synchronization, and operates from –40°C to +105°C ambient. Used in rear-view and surround-view camera systems for real-time sensor fusion.
For engineers reviewing the DS90UB962WRTDRQ1 datasheet, DS90UB962WRTDRQ1 pinout, DS90UB962WRTDRQ1 application, or DS90UB962WRTDRQ1 equivalent, key selection criteria include FPD-Link III RX port count (4), CSI-2 lane scalability (1–4 lanes, up to 1.6 Gbps/lane), adaptive equalization for coax/STP, dual I²C control buses, and functional safety documentation support per ISO 26262.
Technical Context
The DS90UB962WRTDRQ1 integrates four independent FPD-Link III deserializers with adaptive receive equalization for 50-Ω coax or 100-Ω STP cables, enabling robust long-reach video reception. Each RX port maintains a low-latency bidirectional control channel supporting I²C, GPIO, and diagnostics traffic alongside video data.
Its MIPI CSI-2 transmitter complies with D-PHY v1.2 and CSI-2 v1.3, offering programmable lane count (1–4), scalable per-lane data rates (400–1600 Mbps), and configurable synchronous/non-synchronous back-channel modes via MODE pin strapping. Internal frame sync generation enables sub-microsecond inter-sensor timing alignment.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| FPD-Link III RX Ports | 4 independent ports, each supporting 3-Gbps forward channel and bidirectional control over coax or STP |
| CSI-2 Output | Single compliant port with 1–4 configurable data lanes and clock lane; max 1.6 Gbps per lane (832 MHz clock) |
| Operating Temp | –40°C to +105°C ambient; AEC-Q100 Grade 2 qualified for under-hood automotive use |
| Power Supply | VDD11 = 1.1 V ±5%, VDD18 = 1.8 V ±5%, VDDIO = 1.8 V or 3.3 V ±10% |
| Total Power | 999 mW typical at full load: 4× FPD-Link III @ 4.16 Gbps + CSI-2 @ 1.664 Gbps, 4-lane mode |
| I²C Interfaces | Dual Fast-Mode Plus buses (up to 1 Mbps), each with open-drain SCL/SDA and independent pull-up requirements |
| ESD Rating | ±6 kV HBM on FPD-Link III inputs; ±3 kV HBM on all other pins; ±21 kV air discharge on RX inputs |
Pinout & Package
DS90UB962WRTDRQ1 is housed in a 64-pin VQFN package (9.0 mm × 9.0 mm) with exposed thermal pad (DAP) requiring connection to PCB ground plane. Pin functions are validated per TI SNLS573B datasheet Rev B (Sep 2023).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RIN0+ / RIN0− RIN1+ / RIN1− RIN2+ / RIN2− RIN3+ / RIN3− | FPD-Link III differential RX inputs (4 ports) | AC-coupled high-speed video/control interfaces; each pair supports adaptive equalization and bidirectional control channel |
| CSI_CLKP / CSI_CLKN CSI_D0P / CSI_D0N … CSI_D3P / CSI_D3N | MIPI CSI-2 differential TX outputs (1–4 lanes + clock) | Configurable lane count; unused pins must be left as No Connect; supports 400–1600 Mbps per lane |
| I2C_SCL / I2C_SDA I2C_SCL2 / I2C_SDA2 | Dual I²C control bus interfaces | Independent master/target control paths; require external pull-ups to VDDIO; support Fast-Mode Plus (1 Mbps) |
| GPIO0–GPIO7 | Programmable general-purpose I/Os | Configurable as input/output with internal 25-kΩ pulldown; used for sensor sync, diagnostics, and remote register access |
| INTB | Active-low open-drain interrupt output | Signals error conditions (cable fault, loss of lock, register access timeout); requires 4.7-kΩ pull-up to 1.8 V or 3.3 V |
| PDB | Inverted power-down control | Active-high enable; internal 50-kΩ pulldown; must remain low until all supplies stabilize |
| MODE / IDX | Strap configuration inputs | Resistor-divider programmed at power-on to select CSI-2 back-channel mode and I²C device address |
Key Features
| Feature | Design Value |
|---|---|
| Precise multi-camera sync | Internal programmable frame sync generator enables sub-µs inter-sensor timing alignment across all 4 inputs |
| Adaptive cable equalization | Automatically compensates for frequency-dependent loss in coax or STP cables, including aging-related degradation |
| Functional safety support | Documentation available for ISO 26262 ASIL-B system integration; includes diagnostic coverage analysis and failure mode reporting |
| Ultra-low latency path | End-to-end video latency < 5 µs (typical) from FPD-Link III RX input to CSI-2 TX output |
| Flexible power-over-coax (PoC) | Supports single-ended coaxial cabling with integrated power delivery; eliminates separate power wiring in camera modules |
Applications
| Rear View Camera (RVC) | Surround View System (SVS) |
|---|---|
Use Scenario: Single rear-facing camera feeding video to ADAS ECU via coax cable. IC Role / Device Role / Timing Role: Deserializes FPD-Link III stream and converts to MIPI CSI-2 for SoC ingestion; provides GPIO-triggered frame sync. Use Value: Enables cost-effective coax deployment with PoC, reducing harness weight and connector count while maintaining 720p@60Hz fidelity. | Use Scenario: Four independent cameras (front, rear, left, right) simultaneously feeding one central processor. IC Role / Device Role / Timing Role: Aggregates four 3-Gbps FPD-Link III streams into one 4-lane CSI-2 output; synchronizes capture timestamps across all sensors. Use Value: Eliminates need for multiple CSI-2 receivers on SoC; reduces PCB routing complexity and enables pixel-aligned stitching. |
| Driver Monitoring System (DMS) | Forward Vision Camera (FC) |
Use Scenario: In-cabin IR camera capturing driver attention metrics with minimal latency. IC Role / Device Role / Timing Role: Receives serialized video over STP; forwards low-latency CSI-2 stream with embedded I²C/GPIO control for illumination sync. Use Value: Sub-5 µs end-to-end latency ensures real-time eye-tracking responsiveness; dual I²C buses isolate sensor control from host communication. | Use Scenario: High-resolution forward-facing camera for lane detection and object recognition. IC Role / Device Role / Timing Role: Deserializes 1-MP FPD-Link III stream and delivers 4-lane CSI-2 output with precise frame sync to match radar/LiDAR triggers. Use Value: Supports 1MP@30Hz or 720p@60Hz with deterministic timing-critical for sensor fusion timing budgets in L2+ ADAS. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPD-Link III deserializer hub applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90UB964WRTDRQ1 | Same 4-port FPD-Link III hub architecture but adds dual CSI-2 outputs (2× 4-lane) and higher 4.16 Gbps per RX port capability | Required when downstream processor lacks sufficient CSI-2 lanes or needs redundant outputs | Select DS90UB964WRTDRQ1 only if dual CSI-2 outputs or >3 Gbps RX bandwidth per port is needed; otherwise DS90UB962WRTDRQ1 offers optimal cost/power for single-output systems |
| DS90UB954TRGCRQ1 | Quad deserializer with 2× CSI-2 outputs but no internal frame sync generator; supports only 2.1 Gbps per RX port | Suitable for lower-bandwidth SVS where inter-camera sync tolerance >10 µs | Choose DS90UB954TRGCRQ1 for cost-sensitive designs without strict multi-sensor timing requirements; DS90UB962WRTDRQ1 remains preferred for ASIL-B–compliant RVC/DMS with sub-µs sync. |
Compared with DS90UB964WRTDRQ1 and DS90UB954TRGCRQ1, DS90UB962WRTDRQ1 uniquely balances single CSI-2 output simplicity, AEC-Q100 Grade 2 qualification, integrated frame sync, and 3-Gbps per-port performance-making it the optimal choice for production automotive camera hubs where timing determinism, functional safety documentation, and coax/STP flexibility are mandatory.
Availability
DS90UB962WRTDRQ1 is available at Aetrix Electronics and suitable for automotive ADAS, rear-view camera systems, and surround-view applications requiring stable component supply, long-term lifecycle assurance, and AEC-Q100-compliant sourcing.
Supply support for DS90UB962WRTDRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and automotive ICs, with decades of leadership in high-reliability interface solutions.
The DS90UB962WRTDRQ1 belongs to TI's FPD-Link III automotive serializer/deserializer portfolio, designed specifically to enable high-bandwidth, low-latency, and functionally safe camera connectivity in next-generation ADAS and automated driving systems.
FAQ
What is the maximum supported CSI-2 data rate per lane for DS90UB962WRTDRQ1?
The DS90UB962WRTDRQ1 supports CSI-2 data rates of 400 Mbps, 800 Mbps, 1.2 Gbps, 1.5 Gbps, and 1.6 Gbps per lane-corresponding to CSI-2 HS clock frequencies of 184 MHz to 832 MHz. The maximum 1.6 Gbps/lane rate requires a 25-MHz reference clock and is validated for 4-lane operation delivering aggregate bandwidth up to 6.4 Gbps.
Does DS90UB962WRTDRQ1 support power-over-coax (PoC)?
Yes, DS90UB962WRTDRQ1 supports single-ended coaxial cabling with integrated power-over-coax (PoC). Its FPD-Link III RX inputs (RINx+/−) are AC-coupled and compatible with PoC implementations where DC power is superimposed on the coax signal path-enabling simplified camera module wiring without separate power conductors.
How many I²C interfaces does DS90UB962WRTDRQ1 provide, and what are their capabilities?
DS90UB962WRTDRQ1 provides two independent I²C interfaces: primary (I2C_SCL/SDA) and secondary (I2C_SCL2/SDA2). Both support Fast-Mode Plus up to 1 Mbps, operate at VDDIO voltage (1.8 V or 3.3 V), and can function as controller or target. Each requires external pull-up resistors and enables concurrent control of local registers and remote serializers via the bidirectional FPD-Link III control channel.
What is the purpose of the MODE pin on DS90UB962WRTDRQ1?
The MODE pin on DS90UB962WRTDRQ1 is a strap input that selects CSI-2 back-channel operation mode at power-on: MODE option 0 configures non-synchronous back channel, while MODE option 4 enables synchronous back channel. This setting determines how control data is embedded in the CSI-2 stream and affects timing alignment between video and control payloads.
Is DS90UB962WRTDRQ1 pin-compatible with earlier TI FPD-Link III deserializers like DS90UB935-Q1?
No, DS90UB962WRTDRQ1 is not pin-compatible with DS90UB935-Q1 or other single-input deserializers. It is a quad-input hub with 64-pin VQFN packaging and distinct pin mapping-including four FPD-Link III RX pairs, dual I²C buses, and 8 GPIOs. While functionally compatible with DS90UB935-Q1, DS90UB953-Q1, and DS90UB913A-Q1 serializers, hardware redesign is required for migration.
DS90UB962WRTDRQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Deserializer
- Data Rate:
- 3Gbps
- Input Type:
- FPD-Link III, LVDS
- Output Type:
- CSI-2, MIPI
- Number of Inputs:
- -
- Number of Outputs:
- -
- Voltage - Supply:
- 1.045V ~ 1.155V, 1.71V ~ 1.89V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-VQFN (9x9)
DS90UB962WRTDRQ1 FAQ
1.How can I place an order for DS90UB962WRTDRQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90UB962WRTDRQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90UB962WRTDRQ1 reliable?
The price and inventory of DS90UB962WRTDRQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90UB962WRTDRQ1 is usually 5 days.
3.What payment methods are accepted for DS90UB962WRTDRQ1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90UB962WRTDRQ1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90UB962WRTDRQ1?
DS90UB962WRTDRQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90UB962WRTDRQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90UB962WRTDRQ1?
For technical support, including DS90UB962WRTDRQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90UB962WRTDRQ1 requirements.
6.How does Aetrix verify that DS90UB962WRTDRQ1 is sourced from the original manufacturer or authorized distributors?
All DS90UB962WRTDRQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90UB962WRTDRQ1 meets industry standards.
7.What is the process for return or replacement of DS90UB962WRTDRQ1?
All DS90UB962WRTDRQ1 units undergo pre-shipment inspection (PSI). If there is an issue with DS90UB962WRTDRQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90UB962WRTDRQ1 part is unused and in its original packaging.
Return procedure for DS90UB962WRTDRQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90UB962WRTDRQ1 Tags
-
SN65HVS880PWPR
Texas Instruments
-
SN65HVS882PWPR
Texas Instruments
-
FIN3386MTDX
onsemi
-
FIN3385MTDX
onsemi
-
SN65LV1023ARHBR
Texas Instruments
-
SN65LV1023ADBR
Texas Instruments
-
SN65LV1224BDBR
Texas Instruments
-
SN65LVDS93ADGGR
Texas Instruments
-
SN65LVDS93DGGR
Texas Instruments
-
TDES954RGZT
Texas Instruments
-
SN65LV1224BRHBT
Texas Instruments
-
DS90UB914QSQE/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
