My Inquiry
My Account
Texas Instruments DS90UB964TRGCRQ1
- Part No.:
- DS90UB964TRGCRQ1
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 64-VFQFN Exposed Pad
- Datasheet:
-
DS90UB964TRGCRQ1.pdf
- Description:
- IC DESERIALIZER 800MBPS 64VQFN
- Quantity:
- Payment:
- Shipping:
Inventory:1,970
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90UB964TRGCRQ1 from Texas Instruments is an AEC-Q100 Grade 2 automotive-qualified FPD-Link III quad deserializer hub that aggregates up to four 12-bit, 100MHz video streams from image sensors and converts them into two MIPI CSI-2 outputs. It supports HD resolutions (720p/800p/960p) at 30Hz or 60Hz, features adaptive equalization for coaxial/STP cables, and operates from –40°C to +105°C ambient.
For engineers reviewing the DS90UB964TRGCRQ1 datasheet, DS90UB964TRGCRQ1 pinout, DS90UB964TRGCRQ1 application, or DS90UB964TRGCRQ1 equivalent, key selection criteria include multi-camera synchronization capability, dual MIPI CSI-2 port bandwidth scalability (up to 1.6Gbps per lane), Power-over-Coax support, and compatibility with DS90UB933-Q1/DS90UB913A-Q1 serializers in ADAS sensor fusion architectures.
Technical Context
The DS90UB964TRGCRQ1 integrates four independent FPD-Link III deserializers with adaptive receive equalization per channel, enabling robust reception over degraded coaxial or STP cables up to 15m. Each RX port provides a low-latency bidirectional control channel supporting I²C, GPIO, and sensor-side diagnostics.
It implements two fully programmable MIPI D-PHY v1.2 / CSI-2 v1.3 compliant transmitters-each configurable for 1–4 data lanes-with ECC/CRC protection, four virtual channels, and selectable replicate or non-replicate output modes for parallel processing or data logging.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Deserializer Count | 4 independent FPD-Link III RX channels for simultaneous connection to up to four cameras or sensors. |
| CSI-2 Data Rate | Scalable per lane: 400/800/1500/1600 Mbps - enables flexible bandwidth allocation between ports and lane counts. |
| Operating Temp | –40°C to +105°C ambient - qualified per AEC-Q100 Grade 2 for under-hood and exterior automotive camera modules. |
| Cable Interface | Supports single-ended coaxial (with PoC) and 100Ω STP - eliminates need for differential receivers and simplifies EMI-sensitive harness design. |
| I²C Speed | Up to 1 Mbps Fast-mode Plus - allows high-speed configuration and real-time sensor control without dedicated SPI interface. |
| Power Supply | VDD11 = 1.1V ±5%, VDD18 = 1.8V ±5%, VDDIO = 1.8V/3.3V - supports mixed-voltage SoC interfacing and low-noise analog domain separation. |
| Total Power | <1100 mW at full load (1.6Gbps × 2 ports, 4 RX inputs) - enables thermal management in compact 9mm × 9mm VQFN packages. |
Pinout & Package
DS90UB964TRGCRQ1 uses a 64-pin VQFN (RGCR) package with 9.00mm × 9.00mm body size and exposed thermal pad (DAP). Pin functions are validated per TI SNLS500A datasheet Rev. January 2024.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RIN0+ / RIN0− RIN1+ / RIN1− RIN2+ / RIN2− RIN3+ / RIN3− | FPD-Link III RX differential inputs (4 ports) | Accept serialized video/control from compatible serializers; each pair includes AC-coupled internal 100Ω termination and adaptive equalization. |
| CSI0_CLKP/N CSI0_D0P/N–D3P/N CSI1_CLKP/N CSI1_D0P/N–D3P/N | MIPI CSI-2 TX differential outputs (2 ports) | Drive downstream processor CSI-2 receiver; each port supports 1–4 data lanes + clock; configurable via registers for lane count and data type. |
| I2C_SCL / I2C_SDA I2C_SCL2 / I2C_SDA2 | Dual I²C control interfaces | Primary and secondary buses enable isolated configuration of serializer/deserializer clusters or redundant control paths. |
| GPIO0–GPIO7 | Configurable general-purpose I/O | Programmable as input/output for camera sync (e.g., frame trigger), diagnostics (e.g., fault reporting), or sensor-side control signaling. |
| PDB | Inverted power-down control | Active-HIGH enable; internal 50kΩ pulldown ensures safe power-down state at startup; supports low-power standby mode (<100mA total supply current). |
| INTB | Open-drain interrupt output | Active-low signal driven by status registers (e.g., lock loss, CRC error, GPIO event); requires external pullup to VDDIO. |
Key Features
| Feature | Design Value |
|---|---|
| Multi-camera synchronization | Hardware-level timing alignment across all four RX inputs enables precise frame coherency for surround-view stitching and sensor fusion. |
| Dual MIPI CSI-2 ports | Second port provides either additional bandwidth (non-replicate mode) or identical stream replication (replicate mode) for real-time analytics + recording. |
| Adaptive receive equalization | Compensates for cable loss up to 15dB at 1GHz - maintains signal integrity over aging coaxial harnesses without manual tuning. |
| ECC and CRC protection | End-to-end error detection on internal data path and CSI-2 output - prevents corrupted pixel data from propagating to vision processor. |
| Power-over-Coax (PoC) support | Enables single-cable solution for camera power + high-speed data - reduces connector count, weight, and EMI in automotive camera modules. |
Applications
| Surround View Systems (SVS) | Camera Monitoring Systems (CMS) |
|---|---|
Use Scenario: Four exterior cameras feed front/rear/side views into a central domain controller for real-time 360° stitched display. IC Role / Device Role / Timing Role: DS90UB964TRGCRQ1 acts as centralized deserialization hub, aggregating and time-aligning four FPD-Link III streams before delivering synchronized MIPI CSI-2 data to SoC. Use Value: Enables deterministic latency (<22ms lock time) and sub-frame sync accuracy required for seamless stitching without motion artifacts. | Use Scenario: Digital replacement of side mirrors using high-resolution rear-facing and blind-spot cameras routed to display inside cabin. IC Role / Device Role / Timing Role: DS90UB964TRGCRQ1 receives dual 1-MP camera feeds, applies lane-level CSI-2 formatting, and delivers low-jitter video to display processor. Use Value: Supports 60Hz operation at 960p resolution with <5% UI variation - meets ISO 26262 ASIL-B timing requirements for driver assistance displays. |
| Satellite RADAR/LiDAR Fusion | Automotive Security Camera Module |
Use Scenario: Co-located radar and camera units share timing reference and data path to enable synchronized perception for autonomous emergency braking. IC Role / Device Role / Timing Role: DS90UB964TRGCRQ1 provides common clock domain and GPIO-triggered frame sync to align radar echo capture with camera exposure. Use Value: Hardware-based multi-sensor trigger coordination eliminates software-induced jitter - critical for time-of-flight correlation accuracy. | Use Scenario: Front-facing dashcam with tamper detection, HDR imaging, and local video buffering via secondary CSI-2 port. IC Role / Device Role / Timing Role: DS90UB964TRGCRQ1 routes primary video to host SoC while replicating stream to auxiliary encoder or memory controller via CSI-2 Port 1. Use Value: Dual-port architecture enables concurrent display + recording without CPU intervention - reduces system latency and SoC load. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-deserializer hub applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90UB960TRGCRQ1 | Single MIPI CSI-2 output port; no replicate mode; lower max CSI-2 data rate (1.5Gbps vs. 1.6Gbps). | Limited to single-processor architectures; unsuitable for parallel processing or data logging use cases. | Select when cost reduction is prioritized over dual-output flexibility and maximum bandwidth. |
| MAX96712GTJ/V+T | 10-bit, not 12-bit; supports GMSL2, not FPD-Link III; different register map and GPIO architecture. | Requires redesign of serializer side and firmware; incompatible with existing DS90UB9xx-Q1 ecosystem. | Consider only for new GMSL2-based designs where TI FPD-Link III infrastructure is not mandated. |
Compared with DS90UB964TRGCRQ1, DS90UB960TRGCRQ1 sacrifices dual-port flexibility and peak bandwidth for lower BOM cost, while MAX96712GTJ/V+T introduces protocol incompatibility and requalification effort - making DS90UB964TRGCRQ1 the optimal choice for scalable, FPD-Link III–based ADAS hubs requiring time-aligned multi-sensor aggregation.
Availability
DS90UB964TRGCRQ1 is available at Aetrix Electronics and suitable for automotive ADAS, surround-view systems, and camera monitoring systems requiring stable component supply, AEC-Q100 qualification, and long-term production continuity.
Supply support for DS90UB964TRGCRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and automotive ICs, with decades of experience in high-reliability automotive electronics.
The DS90UB964TRGCRQ1 belongs to TI's FPD-Link III serializer/deserializer product line, engineered specifically for high-bandwidth, low-latency, and EMI-resilient camera interconnect in safety-critical automotive vision systems.
FAQ
What is the maximum supported CSI-2 data rate per lane for DS90UB964TRGCRQ1?
The DS90UB964TRGCRQ1 supports CSI-2 data rates of 400 Mbps, 800 Mbps, 1.5 Gbps, and 1.6 Gbps per lane. The 1.6 Gbps rate requires a 25 MHz REFCLK and is validated for operation across the full –40°C to +105°C temperature range. This enables HD 960p video at 60 Hz from each of four sensors with minimal latency.
Does DS90UB964TRGCRQ1 support Power-over-Coax (PoC)?
Yes, DS90UB964TRGCRQ1 supports Power-over-Coax (PoC) operation on all four FPD-Link III RX ports. It is designed to interface directly with TI's DS90UB933-Q1 and DS90UB913A-Q1 serializers in PoC configurations, allowing DC power delivery over the same coaxial cable used for high-speed video and bidirectional control data.
How many MIPI CSI-2 virtual channels does DS90UB964TRGCRQ1 support?
DS90UB964TRGCRQ1 supports four MIPI CSI-2 virtual channels per output port. This allows multiplexing of multiple data streams (e.g., main image, metadata, diagnostic telemetry) over a single physical CSI-2 link - essential for efficient bandwidth utilization in multi-sensor ADAS systems.
What is the function of the CMLOUTP and CMLOUTN pins on DS90UB964TRGCRQ1?
The CMLOUTP and CMLOUTN pins on DS90UB964TRGCRQ1 provide a differential loop-through monitor output of the FPD-Link III forward channel. They enable non-intrusive signal integrity verification at the deserializer input - useful for production test, field diagnostics, and cable health monitoring without disrupting active video transmission.
Is DS90UB964TRGCRQ1 pin-compatible with DS90UB960TRGCRQ1?
No, DS90UB964TRGCRQ1 is not pin-compatible with DS90UB960TRGCRQ1. While both use the same 64-pin VQFN (RGCR) package, their pin assignments differ significantly - particularly for CSI-2 output lanes, GPIO mapping, and power domains. PCB layout and firmware must be redesigned when substituting between these devices.
DS90UB964TRGCRQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Deserializer
- Data Rate:
- 800Mbps
- Input Type:
- FPD-Link III, LVDS
- Output Type:
- CSI-2, MIPI
- Number of Inputs:
- -
- Number of Outputs:
- -
- Voltage - Supply:
- 1.8V, 3.3V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-VQFN (9x9)
DS90UB964TRGCRQ1 FAQ
1.How can I place an order for DS90UB964TRGCRQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90UB964TRGCRQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90UB964TRGCRQ1 reliable?
The price and inventory of DS90UB964TRGCRQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90UB964TRGCRQ1 is usually 5 days.
3.What payment methods are accepted for DS90UB964TRGCRQ1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90UB964TRGCRQ1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90UB964TRGCRQ1?
DS90UB964TRGCRQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90UB964TRGCRQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90UB964TRGCRQ1?
For technical support, including DS90UB964TRGCRQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90UB964TRGCRQ1 requirements.
6.How does Aetrix verify that DS90UB964TRGCRQ1 is sourced from the original manufacturer or authorized distributors?
All DS90UB964TRGCRQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90UB964TRGCRQ1 meets industry standards.
7.What is the process for return or replacement of DS90UB964TRGCRQ1?
All DS90UB964TRGCRQ1 units undergo pre-shipment inspection (PSI). If there is an issue with DS90UB964TRGCRQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90UB964TRGCRQ1 part is unused and in its original packaging.
Return procedure for DS90UB964TRGCRQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90UB964TRGCRQ1 Tags
-
SN65HVS880PWPR
Texas Instruments
-
SN65HVS882PWPR
Texas Instruments
-
FIN3386MTDX
onsemi
-
FIN3385MTDX
onsemi
-
SN65LV1023ARHBR
Texas Instruments
-
SN65LV1023ADBR
Texas Instruments
-
SN65LV1224BDBR
Texas Instruments
-
SN65LVDS93ADGGR
Texas Instruments
-
SN65LVDS93DGGR
Texas Instruments
-
TDES954RGZT
Texas Instruments
-
SN65LV1224BRHBT
Texas Instruments
-
DS90UB914QSQE/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
