Texas Instruments DS90UB964TRGCTQ1
- Part No.:
- DS90UB964TRGCTQ1
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 64-VFQFN Exposed Pad
- Datasheet:
-
DS90UB964TRGCTQ1.pdf
- Description:
- IC DESERIALIZER 800MBPS 64VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:165
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90UB964TRGCTQ1 from Texas Instruments is an AEC-Q100 Grade 2 automotive-qualified FPD-Link III quad deserializer hub that aggregates up to four 12-bit, 100MHz video streams from image sensors and converts them into two MIPI CSI-2 outputs. It supports HD resolutions (720p/800p/960p) at 30Hz or 60Hz, enables multi-camera synchronization, and operates across –40°C to +105°C ambient temperature.
For engineers reviewing the DS90UB964TRGCTQ1 datasheet, DS90UB964TRGCTQ1 pinout, DS90UB964TRGCTQ1 application, or DS90UB964TRGCTQ1 equivalent, this page delivers verified technical context, validated pin functions, confirmed MIPI CSI-2 lane scalability (400–1600 Mbps/lane), real-world ADAS use cases, and two rigorously cross-checked alternative parts for sensor hub designs.
Technical Context
The DS90UB964TRGCTQ1 integrates four independent FPD-Link III deserializers with adaptive equalization for coaxial or STP cable compensation, plus dual MIPI D-PHY v1.2 / CSI-2 v1.3 transmitters supporting 1–4 lanes per port and four virtual channels. Its bidirectional control channel carries I²C, GPIO, and sensor sync signals over the same physical link as video data.
It features CRC/ECC on internal data paths, programmable data types, and two distinct CSI-2 output modes: non-replicate (full bandwidth split across ports) or replicate (identical data on both ports for logging/parallel processing). Power domains include dedicated 1.1V (VDD11), 1.8V (VDD18), and configurable 1.8V/3.3V (VDDIO) supplies.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Interface | Four FPD-Link III RX ports supporting single-ended coaxial (PoC) or differential STP cabling with adaptive equalization |
| Output Interface | Dual MIPI CSI-2 v1.3 compliant TX ports, each configurable for 1–4 data lanes + clock lane at 400–1600 Mbps/lane |
| Resolution Support | Aggregates up to four 1-Megapixel sensors at 720p/800p/960p @ 30Hz or 60Hz frame rate |
| Operating Temp | AEC-Q100 Grade 2: –40°C to +105°C ambient, qualified for automotive ADAS systems |
| ESD Rating | HBM ±4 kV, CDM C6, ISO 10605 ±8 kV contact / ±18 kV air on FPD-Link III inputs |
| Control Interface | Dual I²C buses (primary + secondary) supporting Fast-Mode Plus up to 1 Mbps |
| Package | 64-pin VQFN (9.0 mm × 9.0 mm), thermally enhanced with exposed DAP for PCB ground connection |
Pinout & Package
DS90UB964TRGCTQ1 uses a 64-pin VQFN package (RGC) with 9.0 mm × 9.0 mm body size and thermally optimized exposed die attach pad (DAP) connected to PCB ground plane. Pin functions are validated per TI SNLS500A datasheet Rev. January 2024.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RIN0+ / RIN0− RIN1+ / RIN1− RIN2+ / RIN2− RIN3+ / RIN3− |
FPD-Link III RX differential inputs (4 ports) | Accept serialized video/control from DS90UB913A-Q1/933-Q1 serializers; support AC-coupled coaxial or STP; internal 100Ω differential termination |
| CSI0_CLKP/N CSI0_D0P/N–D3P/N CSI1_CLKP/N CSI1_D0P/N–D3P/N |
MIPI CSI-2 differential TX outputs (2 ports) | Deliver aggregated sensor data to SoC; each port supports 1–4 data lanes + clock; configurable for non-replicate or replicate mode |
| I2C_SCL / I2C_SDA I2C_SCL2 / I2C_SDA2 |
Primary and secondary I²C control interfaces | Enable configuration, status readback, and GPIO control; support Fast-Mode Plus (1 Mbps); open-drain with external pullups to VDDIO |
| GPIO0–GPIO7 | Configurable general-purpose I/Os | Programmable as input/output for camera sync, diagnostics, or serializer control; default pulldown (25kΩ) at power-up |
| PDB | Inverted power-down control | Active-high enable; must remain low until all supplies stabilize; internal 50kΩ pulldown ensures safe power-down state |
| INTB | Active-low interrupt output | Open-drain status flag indicating error conditions (e.g., loss of lock, CRC failure); requires external 4.7kΩ pullup to 1.8V/3.3V |
Key Features
| Feature | Design Value |
|---|---|
| Quad FPD-Link III deserialization | Enables cost-effective aggregation of four independent camera/sensor streams over single coaxial or STP cables - eliminating need for separate routing per sensor |
| Dual MIPI CSI-2 v1.3 outputs | Provides scalable bandwidth (up to 2×4-lane @ 1.6 Gbps/lane) or redundant data replication for safety-critical ADAS logging and parallel processing |
| Multi-camera synchronization | Supports precise timing alignment across all four input streams via hardware-triggered frame sync, essential for surround-view stitching |
| Adaptive receive equalization | Compensates for cable loss in real time - maintains signal integrity over aging coaxial runs up to 15 m without manual tuning |
| Bidirectional control channel | Carries I²C, GPIO, and sensor commands over same physical link as video - eliminates need for separate control wiring and reduces connector count |
Applications
| Surround View Systems (SVS) | Camera Monitoring Systems (CMS) |
|---|---|
Use Scenario: Four fisheye cameras mounted at vehicle corners feed simultaneous video to central ECU for real-time 360° stitched display. IC Role / Device Role / Timing Role: DS90UB964TRGCTQ1 acts as centralized deserializer hub, synchronizing frame capture and aggregating streams into dual CSI-2 outputs for GPU or vision processor ingestion. Use Value: Enables deterministic latency (<22 ms lock time) and sub-microsecond inter-sensor skew control - critical for seamless image stitching and low-latency driver feedback. |
Use Scenario: Digital replacement of side mirrors using high-resolution rear/side cameras routed to in-cabin display with minimal wiring harness complexity. IC Role / Device Role / Timing Role: DS90UB964TRGCTQ1 receives serialized video from mirror-mounted sensors and delivers time-aligned MIPI CSI-2 data to display controller or SoC with ECC-protected data path. Use Value: Reduces cable weight and EMI by replacing LVDS or parallel RGB with FPD-Link III over coax; PoC capability powers remote cameras through same cable. |
| Satellite RADAR Sensor Fusion | LIDAR Time-of-Flight Modules |
Use Scenario: Integrating radar echo data with camera feeds for object classification and trajectory prediction in autonomous driving stacks. IC Role / Device Role / Timing Role: DS90UB964TRGCTQ1 provides synchronized timestamping and packetized delivery of camera frames alongside radar metadata via its bidirectional control channel. Use Value: Hardware-level frame sync and virtual channel tagging allow precise temporal correlation between optical and RF sensing modalities - improving fusion accuracy. |
Use Scenario: High-speed LIDAR point cloud generation requiring precise trigger coordination with auxiliary imaging for depth-color registration. IC Role / Device Role / Timing Role: DS90UB964TRGCTQ1 accepts triggered video bursts from LIDAR-adjacent imagers and forwards aligned frames via CSI-2 with embedded sync markers. Use Value: Eliminates external timing controllers by embedding GPIO-based trigger distribution and frame-ready signaling within the deserializer's control channel. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad deserializer hub applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90UB960TRGCTQ1 | Single MIPI CSI-2 output port (vs. dual); no replicate mode; lower max CSI-2 data rate (1.5 Gbps/lane vs. 1.6 Gbps) | Suitable for cost-sensitive ADAS systems needing only one downstream processor interface | Select when dual-port redundancy or maximum bandwidth is unnecessary - reduces BOM cost and layout complexity |
| MAX96712GTJ/V+T | GMSL2 interface (not FPD-Link III); supports longer cable reach (15 m coax @ 4 Gbps); different register map and GPIO architecture | Preferred for high-bandwidth LIDAR or thermal camera integration where GMSL2 ecosystem compatibility matters | Choose when migrating from existing GMSL2 infrastructure or requiring higher forward-channel throughput than FPD-Link III offers |
Compared with DS90UB964TRGCTQ1, DS90UB960TRGCTQ1 reduces functional redundancy but lowers system cost, while MAX96712GTJ/V+T shifts to GMSL2 for extended reach and higher bandwidth - neither is pin-compatible, and both require board redesign and firmware adaptation.
Availability
DS90UB964TRGCTQ1 is available at Aetrix Electronics and suitable for automotive ADAS, surround-view systems, and camera monitoring systems requiring stable component supply, AEC-Q100 compliance, and long-term production continuity.
Supply support for DS90UB964TRGCTQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and automotive ICs, with deep expertise in high-speed serial interface solutions and functional safety design.
The DS90UB964TRGCTQ1 belongs to TI's FPD-Link III automotive serializer/deserializer product line, engineered specifically for high-reliability, low-latency video aggregation in next-generation ADAS and autonomous driving architectures.
FAQ
What is the primary function of the DS90UB964TRGCTQ1 in an automotive ADAS system?
The DS90UB964TRGCTQ1 serves as a quad FPD-Link III deserializer hub that aggregates video data from up to four independent image sensors - such as surround-view cameras - and converts it into two MIPI CSI-2 outputs for processing by an SoC or vision processor. Its role includes multi-camera synchronization, adaptive cable equalization, and bidirectional control channel management, making it foundational for real-time, safety-critical ADAS applications.
Does the DS90UB964TRGCTQ1 support Power-over-Coax (PoC) operation?
Yes, the DS90UB964TRGCTQ1 supports Power-over-Coax (PoC) operation on its FPD-Link III RX ports (RIN0± through RIN3±), enabling DC power delivery to compatible serializers like DS90UB913A-Q1 over the same coaxial cable used for high-speed video and control data - reducing wiring complexity and connector count in automotive camera modules.
What MIPI CSI-2 data rates does the DS90UB964TRGCTQ1 support per lane?
The DS90UB964TRGCTQ1 supports scalable MIPI CSI-2 data rates of 400 Mbps, 800 Mbps, 1.5 Gbps, and 1.6 Gbps per data lane across both CSI-2 output ports. These rates are selectable via register configuration and depend on reference clock frequency (23 MHz for ≤1.5 Gbps; 25 MHz for 1.6 Gbps), ensuring flexibility for varying resolution and frame-rate requirements.
How many GPIOs does the DS90UB964TRGCTQ1 provide, and what are their key capabilities?
The DS90UB964TRGCTQ1 provides eight GPIOs (GPIO0–GPIO7), each configurable as input or output via register control. They support camera synchronization (e.g., frame start/trigger), diagnostics (e.g., fault reporting), and serializer-side control. At power-up, all GPIOs default to disabled with internal 25kΩ pulldowns, and they operate at either 1.8V or 3.3V logic levels depending on VDDIO configuration.
Is the DS90UB964TRGCTQ1 compatible with DS90UB933-Q1 and DS90UB913A-Q1 serializers?
Yes, the DS90UB964TRGCTQ1 is explicitly designed for interoperability with DS90UB933-Q1 and DS90UB913A-Q1 serializers. TI documentation confirms full protocol compatibility, including FPD-Link III forward/back channel timing, control message framing, and GPIO pass-through functionality - enabling seamless integration in multi-sensor automotive camera systems.
DS90UB964TRGCTQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Deserializer
- Data Rate:
- 800Mbps
- Input Type:
- FPD-Link III, LVDS
- Output Type:
- CSI-2, MIPI
- Number of Inputs:
- -
- Number of Outputs:
- -
- Voltage - Supply:
- 1.8V, 3.3V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-VQFN (9x9)
DS90UB964TRGCTQ1 FAQ
1.How can I place an order for DS90UB964TRGCTQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90UB964TRGCTQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90UB964TRGCTQ1 reliable?
The price and inventory of DS90UB964TRGCTQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90UB964TRGCTQ1 is usually 5 days.
3.What payment methods are accepted for DS90UB964TRGCTQ1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90UB964TRGCTQ1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90UB964TRGCTQ1?
DS90UB964TRGCTQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90UB964TRGCTQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90UB964TRGCTQ1?
For technical support, including DS90UB964TRGCTQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90UB964TRGCTQ1 requirements.
6.How does Aetrix verify that DS90UB964TRGCTQ1 is sourced from the original manufacturer or authorized distributors?
All DS90UB964TRGCTQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90UB964TRGCTQ1 meets industry standards.
7.What is the process for return or replacement of DS90UB964TRGCTQ1?
All DS90UB964TRGCTQ1 units undergo pre-shipment inspection (PSI). If there is an issue with DS90UB964TRGCTQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90UB964TRGCTQ1 part is unused and in its original packaging.
Return procedure for DS90UB964TRGCTQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90UB964TRGCTQ1 Tags

-
SN65HVS880PWPR
Texas Instruments

-
SN65HVS882PWPR
Texas Instruments

-
FIN3386MTDX
onsemi

-
FIN3385MTDX
onsemi

-
SN65LV1023ARHBR
Texas Instruments

-
SN65LV1023ADBR
Texas Instruments

-
SN65LV1224BDBR
Texas Instruments

-
SN65LVDS93ADGGR
Texas Instruments

-
SN65LVDS93DGGR
Texas Instruments

-
TDES954RGZT
Texas Instruments

-
SN65LV1224BRHBT
Texas Instruments

-
DS90UB914QSQE/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

