My Inquiry
My Account
Texas Instruments DS90UH925ATRHSJQ1
- Part No.:
- DS90UH925ATRHSJQ1
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
DS90UH925ATRHSJQ1.pdf
- Description:
- IC SERIAL/DESERIAL 24BIT 48WQFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,751
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90UH925ATRHSJQ1 from Texas Instruments is an automotive-grade FPD-Link III serializer IC that converts 24-bit RGB digital video (720p), HS/VS/DE control signals, and stereo I2S audio into a single AC-coupled 100 Ω STP serial link operating up to 2.975 Gbps. It integrates HDCP 1.3 cipher engine with on-chip key storage and supports 5–85 MHz PCLK across 1.8 V or 3.3 V LVCMOS I/O. It is designed for secure in-vehicle display interconnects between graphics processors and touch-screen displays.
For engineers reviewing the DS90UH925ATRHSJQ1 datasheet, DS90UH925ATRHSJQ1 pinout, DS90UH925ATRHSJQ1 application, or DS90UH925ATRHSJQ1 equivalent, this page delivers verified technical context, exact pin functions, real-world timing constraints (e.g., 2 transitions/130 PCLK limit on DE/HS), HDCP repeater capability, and validated alternatives for automotive display system design.
Technical Context
The DS90UH925ATRHSJQ1 implements a 35-bit symbol-based FPD-Link III forward channel with embedded clock, DC-balanced scrambling, and HDCP encryption applied before serialization. It accepts parallel RGB888 + HS/VS/DE + I2S stereo inputs and outputs differential CML signals (DOUT+/DOUT−) compliant with 100 Ω AC-coupled STP cabling up to 10 meters.
Its bidirectional control interface supports full-duplex I²C communication and HDCP key exchange over the same serial link, while dedicated pins (INTB, REM_INTB) enable remote interrupt mirroring. The device features programmable control signal filtering, MODE_SEL-configurable 18-/24-bit color modes, and dual-supply operation (VDD33 = 3.0–3.6 V, VDDIO = 1.71–1.89 V or 3.0–3.6 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| PCLK Range | 5–85 MHz - Defines minimum frame rate support and maximum pixel throughput for 720p RGB888 video. |
| Serial Line Rate | 525 Mbps to 2.975 Gbps - Enables AC-coupled transmission over single 100 Ω STP pair with embedded clock recovery. |
| HDCP Support | HDCP 1.3 with on-chip key storage - Provides content protection without external crypto controller; keys never exposed externally. |
| I/O Voltage Options | VDDIO = 1.8 V ±5% or 3.3 V - Allows direct interfacing with both low-voltage GPUs and legacy 3.3 V controllers. |
| ESD Rating | ±8 kV HBM, ±8 kV ISO 10605 - Meets AEC-Q100 Grade 2 requirements for automotive infotainment environments. |
| Power-down Current | IDDS2 ≤ 2 mA (VDD33) + 150 μA (VDDIO) - Enables ultra-low standby power when PDB = L and LVCMOS inputs are grounded. |
| Serializer Output | DOUT+/DOUT− CML, VOD = 1160–1340 mVpp into 100 Ω - Ensures robust signal integrity over 10 m cable at 78 MHz PCLK. |
Pinout & Package
DS90UH925ATRHSJQ1 uses a 48-pin WQFN package (7.0 mm × 7.0 mm, 0.4 mm pitch) with exposed thermal pad (DAP) requiring ≥9 vias to ground plane. Pin functions are validated per TI SNLS481 datasheet Rev. JUNE 2014.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| R[7:0], G[7:0], B[7:0] | Parallel RGB data inputs | Accept 24-bit RGB888 video; each group has internal pull-down; R0/G0/B0 support GPIO/GPO functions in 18-bit mode. |
| HS, VS, DE | Video timing control inputs | LVCMOS sync signals with configurable filter: max 2 transitions/130 PCLK cycles when enabled; min pulse width = 3 PCLK. |
| PCLK | Pixel clock input | Strobe edge configurable via RFB register; supports 5–85 MHz; jitter tolerance = 0.4–0.6 UI for BER ≤10⁻¹⁰. |
| I2S_CLK, I2S_WC, I2S_DA | Stereo audio interface inputs | Support 16-/18-/24-bit I2S; I2S_WC/I2S_DA double as GPO_REG7/GPO_REG6; I2S_DB available in 18-bit mode. |
| DOUT+, DOUT− | FPD-Link III serial outputs | CML differential outputs requiring 0.1 µF AC coupling; VOD = 1250 mVpp typ into 100 Ω load. |
| SCL, SDA | I²C control bus interface | Open-drain, 3.3 V tolerant; support standard/fast mode (100/400 kHz); require 4.7 kΩ external pull-up to VDD33. |
| INTB, REM_INTB | Interrupt outputs | INTB signals local events (e.g., lock loss); REM_INTB mirrors INTB_IN from downstream deserializer after lock achieved. |
| PDB | Power-down control input | PDB = L forces shutdown: PLL off, drivers high-Z, IDD minimized; PDB = H enables normal operation. |
Key Features
| Feature | Design Value |
|---|---|
| HDCP 1.3 cipher engine | On-chip encryption with non-volatile key storage eliminates need for external security IC and prevents key exposure during handshake. |
| Backward compatibility | Interoperates with FPD-Link II deserializers (DS90UR906Q/DS90UR908Q), enabling migration from legacy systems without redesign. |
| AC-coupled STP support | Enables use of cost-effective, lightweight 100 Ω shielded twisted-pair cables up to 10 m-reducing EMI and eliminating DC skew issues. |
| Dedicated remote interrupt mirroring | REM_INTB pin directly reflects INTB_IN status from DS90UH926Q deserializer, simplifying fault reporting in multi-display architectures. |
| Programmable control signal filtering | Configurable DE/HS/VS transition limits (2/130 PCLK) reduce false triggering in noisy automotive environments while preserving video fidelity. |
| Low-power modes | Auto power-down mode cuts supply current to <2.4 mA (VDD33) + 150 μA (VDDIO), critical for always-on display subsystems. |
Applications
| Automotive Touch Screen Display | Automotive Navigation Display |
|---|---|
Use Scenario: High-resolution 720p LCD panel mounted in center console, driven by SoC GPU via short PCB trace. IC Role / Device Role / Timing Role: Serializer converting parallel RGB + I2S audio + sync signals into single FPD-Link III stream for EMI-robust routing through vehicle harness. Use Value: Eliminates 30+ parallel traces; supports HDCP-protected map/video streaming; enables 10 m cable run with <0.3 UI jitter at 78 MHz PCLK. |
Use Scenario: Cluster-integrated navigation screen receiving encrypted video from head-unit processor across dashboard harness. IC Role / Device Role / Timing Role: Secure serializer embedding HDCP keys and transmitting encrypted video/audio over single STP pair to remote deserializer. Use Value: Meets AEC-Q100 Grade 2 temp range (−40°C to +105°C); withstands >8 kV ESD per ISO 10605; supports 131×PCLK lock time for stable startup. |
| Rear Seat Entertainment System | HDCP Repeater Node |
Use Scenario: Dual-screen rear-seat system where head-unit video is split and distributed to left/right displays. IC Role / Device Role / Timing Role: Primary serializer feeding two downstream DS90UH926Q deserializers via passive splitter or active repeater topology. Use Value: Backward-compatible with FPD-Link II receivers allows reuse of existing display modules; I2S stereo support enables synchronized audio playback. |
Use Scenario: In-vehicle infotainment hub acting as HDCP repeater between source (e.g., HDMI dongle) and display (e.g., headrest monitor). IC Role / Device Role / Timing Role: HDCP-compliant serializer performing key re-authentication and encrypted retransmission of protected content. Use Value: On-chip HDCP engine handles full repeater authentication flow without host CPU involvement; supports HDCP 1.3 compliance testing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPD-Link III serializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90UH925AQ-Q1 | Same silicon, identical electrical specs and pinout; differs only in tape-and-reel packaging (TR) vs. tray (Q1). | No functional difference; TR variant optimized for automated SMT assembly; Q1 for prototyping or low-volume hand-soldering. | Select DS90UH925ATRHSJQ1 for volume production with pick-and-place; choose DS90UH925AQ-Q1 for evaluation or small-batch builds. |
| DS90UH927TRHSJQ1 | Higher-speed variant supporting 1080p (1920×1080) at 60 Hz; adds 4-lane MIPI DSI input; no HDCP engine; different pinout and register map. | Targeted at premium displays requiring >720p resolution; lacks built-in HDCP, requiring external security IC for protected content. | Use DS90UH927TRHSJQ1 only when 1080p bandwidth (>3.75 Gbps) and MIPI input are required; retain DS90UH925ATRHSJQ1 for HDCP-secured 720p systems. |
Compared with DS90UH925AQ-Q1, DS90UH925ATRHSJQ1 offers identical functionality in tape-and-reel format for production efficiency, while DS90UH927TRHSJQ1 trades HDCP for higher resolution and MIPI support-making it unsuitable as a drop-in replacement but viable for non-HDCP 1080p upgrades.
Availability
DS90UH925ATRHSJQ1 is available at Aetrix Electronics and suitable for automotive touch screen displays, navigation systems, and rear seat entertainment requiring stable component supply, AEC-Q100 qualification, and long-term lifecycle support.
Supply support for DS90UH925ATRHSJQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity solutions for automotive, industrial, and communications markets.
The DS90UH925ATRHSJQ1 belongs to TI's FPD-Link III automotive serializer family, engineered specifically for secure, high-reliability video transport in safety-critical vehicle displays with integrated HDCP and AEC-Q100 Grade 2 compliance.
FAQ
What is the maximum supported pixel clock frequency for DS90UH925ATRHSJQ1?
The DS90UH925ATRHSJQ1 supports PCLK frequencies from 5 MHz to 85 MHz, enabling full 720p (1280×720) RGB888 video at 60 Hz. At 85 MHz, the serialized line rate reaches 2.975 Gbps, which is the maximum specified for reliable AC-coupled transmission over 100 Ω STP cable up to 10 meters. Operation beyond 85 MHz is not supported.
Does DS90UH925ATRHSJQ1 support HDCP key updates in the field?
No, DS90UH925ATRHSJQ1 contains fixed HDCP 1.3 keys stored in on-chip non-volatile memory and does not support field-updatable keys. Key exchange occurs securely over the FPD-Link III bidirectional control channel during authentication, but the root keys themselves are factory-programmed and immutable. This design ensures tamper resistance per automotive security requirements.
Can DS90UH925ATRHSJQ1 interface with a 1.8 V GPU without level shifters?
Yes, DS90UH925ATRHSJQ1 supports 1.8 V ±5% LVCMOS I/O via its VDDIO supply pin. When VDDIO is set to 1.8 V, all parallel inputs (R[7:0], G[7:0], B[7:0], HS, VS, DE, PCLK, I2S signals) operate at 1.8 V logic levels with VIH = 0.65×VDDIO and VIL = 0.35×VDDIO-enabling direct connection to 1.8 V graphics processors without external level translation.
What is the purpose of the CMF pin on DS90UH925ATRHSJQ1?
The CMF (Common Mode Filter) pin on DS90UH925ATRHSJQ1 provides access to the center tap of the internal 100 Ω differential termination. A 0.1 µF capacitor must be connected from CMF to ground to suppress common-mode noise-especially critical in high-EMI automotive environments. This improves signal integrity and reduces radiated emissions on the FPD-Link III serial output.
Is DS90UH925ATRHSJQ1 compatible with FPD-Link II deserializers?
Yes, DS90UH925ATRHSJQ1 includes backward compatibility modes that allow interoperability with FPD-Link II deserializers such as DS90UR906Q and DS90UR908Q. This is achieved through configurable symbol mapping and reduced line rate negotiation, enabling gradual system upgrades without replacing existing display modules-though HDCP and I2S audio features may be limited in FPD-Link II mode.
DS90UH925ATRHSJQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Function:
- Serializer
- Data Rate:
- 2.975Gbps
- Input Type:
- LVCMOS
- Output Type:
- FPD-Link III, LVDS
- Number of Inputs:
- 31
- Number of Outputs:
- 1
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-WQFN (7x7)
DS90UH925ATRHSJQ1 FAQ
1.How can I place an order for DS90UH925ATRHSJQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90UH925ATRHSJQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90UH925ATRHSJQ1 reliable?
The price and inventory of DS90UH925ATRHSJQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90UH925ATRHSJQ1 is usually 5 days.
3.What payment methods are accepted for DS90UH925ATRHSJQ1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90UH925ATRHSJQ1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90UH925ATRHSJQ1?
DS90UH925ATRHSJQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90UH925ATRHSJQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90UH925ATRHSJQ1?
For technical support, including DS90UH925ATRHSJQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90UH925ATRHSJQ1 requirements.
6.How does Aetrix verify that DS90UH925ATRHSJQ1 is sourced from the original manufacturer or authorized distributors?
All DS90UH925ATRHSJQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90UH925ATRHSJQ1 meets industry standards.
7.What is the process for return or replacement of DS90UH925ATRHSJQ1?
All DS90UH925ATRHSJQ1 units undergo pre-shipment inspection (PSI). If there is an issue with DS90UH925ATRHSJQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90UH925ATRHSJQ1 part is unused and in its original packaging.
Return procedure for DS90UH925ATRHSJQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90UH925ATRHSJQ1 Tags
-
SN65HVS880PWPR
Texas Instruments
-
SN65HVS882PWPR
Texas Instruments
-
FIN3386MTDX
onsemi
-
FIN3385MTDX
onsemi
-
SN65LV1023ARHBR
Texas Instruments
-
SN65LV1023ADBR
Texas Instruments
-
SN65LV1224BDBR
Texas Instruments
-
SN65LVDS93ADGGR
Texas Instruments
-
SN65LVDS93DGGR
Texas Instruments
-
TDES954RGZT
Texas Instruments
-
SN65LV1224BRHBT
Texas Instruments
-
DS90UB914QSQE/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
