My Inquiry
My Account
Texas Instruments DS90UR124IVS/NOPB
- Part No.:
- DS90UR124IVS/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 64-TQFP
- Datasheet:
-
DS90UR124IVS/NOPB.pdf
- Description:
- IC SER/DESER 5-43MHZ 24B 64-TQFP
- Quantity:
- Payment:
- Shipping:
Inventory:3,900
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90UR124IVS/NOPB from Texas Instruments is an automotive-grade FPD-Link II deserializer IC that converts a single LVDS serial stream into a 24-bit LVCMOS parallel interface (RGB666 + HS/VS/DE + 3 GP) for display systems. It operates from 5MHz to 43MHz pixel clock, supports AC-coupled transmission over shielded twisted-pair up to 10 m, and features embedded clock recovery with DC-balanced encoding. It is used in instrument cluster and central infotainment displays requiring AEC-Q100 Grade 2 compliance.
For engineers reviewing the DS90UR124IVS/NOPB datasheet, DS90UR124IVS/NOPB pinout, DS90UR124IVS/NOPB application, or DS90UR124IVS/NOPB equivalent, this page delivers verified technical context, pin-level design meaning, automotive timing role clarity, and validated alternative options - all grounded in TI's SNLS231P production data sheet (August 2024 revision).
Technical Context
The DS90UR124IVS/NOPB implements a PLL-based clock recovery architecture that extracts timing from the incoming FPD-Link II LVDS stream without requiring an external reference clock. Its DC-balance decoder and proprietary random lock enable robust AC-coupled operation and eliminate inter-symbol interference across long cables.
It provides three independent LVCMOS output groups (ROUT[7:0], [15:8], [23:16]) with programmable progressive turn-on (PTOSEL), slew rate control (SLEW), and per-group setup/hold timing offsets (±1–2 UI). The LOCK signal indicates PLL lock status, while BISTEN/BISTM enable @Speed BIST validation of the full serial link path.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | FPD-Link II deserializer converting 1-lane LVDS serial input to 24-bit LVCMOS parallel output (RGB666 + sync + 3 GP) |
| Pixel Clock Range | 5 MHz to 43 MHz - defines supported display resolution and refresh rate envelope (e.g., WVGA@60Hz to SVGA@60Hz) |
| Supply Voltage | 3.3 V ±10% - requires stable low-noise LDO; dual-domain (analog/digital) VDD pins must be independently decoupled |
| Operating Temperature | –40°C to +105°C - qualified for under-hood and dashboard automotive environments per AEC-Q100 Grade 2 |
| ESD Rating | ≥±8 kV HBM on all pins - meets ISO 10605 for automotive ESD robustness without external protection |
| LVDS Input Sensitivity | ±50 mV differential threshold - ensures reliable lock under cable loss and jitter up to 0.25 UI tolerance window |
| Power Consumption | 85–105 mA typical at 43 MHz - scales with pattern and SLEW setting; drops to 50 µA in RPWDNB power-down mode |
Pinout & Package
DS90UR124IVS/NOPB uses a 64-pin TQFP (PAG package), 10.00 mm × 10.00 mm body size, with exposed thermal pad (not electrically connected). Pin functions are defined per TI SNLS231P Rev. August 2024.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RIN+, RIN− | LVDS differential input pair | AC-coupled (100 nF) termination to 100 Ω; accepts embedded-clock FPD-Link II stream; no external REFCLK needed |
| ROUT[23:0] | 24-bit LVCMOS parallel output bus | Grouped into three 8-bit banks (GRP1–GRP3); each group has independent timing alignment via PTOSEL/SLEW |
| RCLK | Recovered parallel clock output | Strobe edge set by RRFB; used to latch ROUT[23:0]; tri-stated when LOCK = L or REN = L |
| LOCK | PLL lock status indicator | Open-drain LVCMOS output; HIGH = PLL locked and ROUT/RCLK valid; LOW = unlocked → outputs tri-stated |
| RPWDNB | Receiver power-down control | Active-low; asserts tri-state on all outputs and shuts down PLL to reduce current to 50 µA |
| REN | Parallel output enable | Active-high; enables ROUT[23:0]/RCLK when LOCK = H; disables (tri-state) when LOW, preserving PLL lock |
| PTOSEL | Progressive Turn-On mode select | H = grouped switching (±1–2 UI stagger); L = spread-mode (±1 UI stagger) - reduces simultaneous switching noise (SSN) |
| BISTEN, BISTM | @Speed BIST control inputs | Enable link-level bit-error testing; BISTM selects reporting mode (cycle-by-cycle vs. accumulated count on ROUT[7:0]) |
Key Features
| Feature | Design Value |
|---|---|
| Embedded clock recovery | Eliminates need for separate reference clock routing; simplifies PCB layout and reduces EMI from clock distribution |
| DC-balanced encoding | Enables AC coupling over long cables (up to 10 m STP); prevents baseline wander and allows transformer isolation |
| Programmable PTO (Progressive Turn-On) | Staggers LVCMOS output group switching to cut peak current and system-level SSN by >50% vs. synchronous toggle |
| @Speed BIST | Validates end-to-end LVDS link integrity in-system without external test equipment; PASS pin gives pass/fail result |
| AEC-Q100 Grade 2 qualification | Guarantees operation from –40°C to +105°C ambient; includes stress testing for automotive reliability and lifetime requirements |
Applications
| Automotive Instrument Cluster | Central Infotainment Display |
|---|---|
Use Scenario: High-reliability digital gauge rendering with real-time vehicle data overlay (speed, RPM, warnings). IC Role / Device Role / Timing Role: Deserializes graphics data from ECU or video processor over single FPD-Link II lane; recovers pixel clock and drives RGB666 interface to TFT panel. Use Value: Reduces cable harness weight and connector pin count vs. parallel RGB; maintains timing integrity across temperature and vibration. |
Use Scenario: 7–10 inch touchscreen display in center stack, driven by SoC with limited LVDS lanes. IC Role / Device Role / Timing Role: Receives compressed 24-bit video stream via shielded twisted-pair; outputs synchronized LVCMOS RGB + DE/HS/VS to display controller. Use Value: Enables high-fidelity video transport over cost-effective cabling while meeting automotive EMI and safety standards. |
| Heads-Up Display (HUD) | Remote Camera Display Link |
Use Scenario: Compact projection-based HUD with tight space constraints and thermal sensitivity. IC Role / Device Role / Timing Role: Converts serialized video from image processor into precise parallel timing signals for micro-display driver IC. Use Value: Supports low-jitter, low-skew pixel delivery critical for optical alignment; operates reliably at 105°C ambient. |
Use Scenario: Rear-view or surround-view camera feed routed to display unit through firewall or chassis barrier. IC Role / Device Role / Timing Role: Terminates FPD-Link II serial stream from remote serializer (e.g., DS90UR241-Q1); reconstructs full 24-bit video bus with embedded sync. Use Value: Provides galvanic isolation via AC-coupled LVDS, immune to ground loop noise and voltage offset between domains. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPD-Link II deserializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90UR124AQMA/NOPB | Same silicon, automotive-grade (Q1) variant with enhanced ESD (±10 kV contact) and extended qualification traceability. | Required for new automotive designs targeting ASIL-B or higher functional safety alignment. | Select DS90UR124AQMA/NOPB when full AEC-Q100 requalification documentation and extended ESD margin are mandatory. |
| DS90UB925QSQ/NOPB | FPD-Link III deserializer; supports higher bandwidth (up to 100 MHz), bidirectional control channel, and I2C passthrough. | Suitable for next-gen displays with higher resolution or touch feedback integration; not backward-compatible with FPD-Link II. | Choose DS90UB925QSQ/NOPB only when upgrading to FPD-Link III ecosystem; requires serializer change and layout revision. |
Compared with DS90UR124AQMA/NOPB, the DS90UR124IVS/NOPB offers identical core functionality and timing but with standard Q1 qualification-ideal for cost-sensitive Tier 2 automotive modules. Against DS90UB925QSQ/NOPB, it provides proven FPD-Link II interoperability and lower system complexity where 43 MHz bandwidth suffices.
Availability
DS90UR124IVS/NOPB is available at Aetrix Electronics and suitable for automotive instrument clusters, central infotainment displays, and heads-up displays requiring stable component supply, AEC-Q100-compliant sourcing, and long-term production continuity.
Supply support for DS90UR124IVS/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and automotive electronics, with decades of experience in high-reliability interface solutions.
The DS90URxxx-Q1 product line was designed specifically for automotive display links, emphasizing EMI resilience, cable drive capability, and AEC-Q100 compliance - enabling compact, robust, and cost-efficient video transport in harsh environments.
FAQ
What is the primary function of the DS90UR124IVS/NOPB in an automotive display system?
The DS90UR124IVS/NOPB serves as an FPD-Link II deserializer that receives a single LVDS serial stream carrying 24-bit video data (RGB666 + sync + 3 GP) and reconstructs it into a parallel LVCMOS interface for driving TFT displays. It performs embedded clock recovery, DC-balanced decoding, and provides programmable output timing - all within an AEC-Q100 Grade 2 qualified package. This enables simplified cabling and reliable video transport in instrument clusters and infotainment units.
Does the DS90UR124IVS/NOPB require an external reference clock?
No, the DS90UR124IVS/NOPB does not require an external reference clock. It implements a fully integrated PLL-based clock recovery circuit that extracts timing directly from the incoming FPD-Link II LVDS serial stream. This eliminates the need for clock distribution traces, reduces EMI, and simplifies system design - a key advantage confirmed in TI's SNLS231P datasheet Section 3 and Figure 6-1.
How does the DS90UR124IVS/NOPB support long-cable applications up to 10 meters?
The DS90UR124IVS/NOPB supports 10-meter shielded twisted-pair operation through DC-balanced encoding (enabling AC coupling), receiver input tolerance of ±0.25 UI, and compatibility with pre-emphasis-enabled serializers like DS90UR241-Q1. Its LVDS input stage is optimized for low jitter sensitivity, and its internal equalization maintains eye opening across lossy channels - all validated per TI's SNLS231P electrical specs (Sections 5.5, 5.8) and application diagrams.
What is the role of the LOCK pin on the DS90UR124IVS/NOPB?
The LOCK pin on the DS90UR124IVS/NOPB is an open-drain LVCMOS output indicating PLL lock status: HIGH means the internal PLL has successfully recovered a stable clock from the LVDS input and ROUT/RCLK outputs are valid; LOW means unlocked, forcing all parallel outputs into tri-state. This signal is essential for system-level synchronization and fault detection - documented in Table 4-2 and Section 5.8 of the DS90UR124-Q1 datasheet.
Can the DS90UR124IVS/NOPB be used with non-TI serializers?
Yes, the DS90UR124IVS/NOPB is compatible with any FPD-Link II-compliant serializer meeting the same electrical and protocol specifications - including TI's DS90UR241-Q1 and third-party equivalents certified to the FPD-Link II standard. Interoperability depends on matching pixel clock range (5–43 MHz), DC-balance compliance, and LVDS signal integrity; TI confirms backward compatibility with DS90C241/DS90C124 in SNLS231P Section 1.
DS90UR124IVS/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-TQFP
- Packaging:
- Tray
- Product Status:
- Active
- Function:
- Deserializer
- Data Rate:
- 1.03Gbps
- Input Type:
- FPD-Link II, LVDS
- Output Type:
- LVCMOS
- Number of Inputs:
- 1
- Number of Outputs:
- 24
- Voltage - Supply:
- 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-TQFP (10x10)
DS90UR124IVS/NOPB FAQ
1.How can I place an order for DS90UR124IVS/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90UR124IVS/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90UR124IVS/NOPB reliable?
The price and inventory of DS90UR124IVS/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90UR124IVS/NOPB is usually 5 days.
3.What payment methods are accepted for DS90UR124IVS/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90UR124IVS/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90UR124IVS/NOPB?
DS90UR124IVS/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90UR124IVS/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90UR124IVS/NOPB?
For technical support, including DS90UR124IVS/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90UR124IVS/NOPB requirements.
6.How does Aetrix verify that DS90UR124IVS/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90UR124IVS/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90UR124IVS/NOPB meets industry standards.
7.What is the process for return or replacement of DS90UR124IVS/NOPB?
All DS90UR124IVS/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90UR124IVS/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90UR124IVS/NOPB part is unused and in its original packaging.
Return procedure for DS90UR124IVS/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90UR124IVS/NOPB Tags
-
SN65HVS880PWPR
Texas Instruments
-
SN65HVS882PWPR
Texas Instruments
-
FIN3386MTDX
onsemi
-
FIN3385MTDX
onsemi
-
SN65LV1023ARHBR
Texas Instruments
-
SN65LV1023ADBR
Texas Instruments
-
SN65LV1224BDBR
Texas Instruments
-
SN65LVDS93ADGGR
Texas Instruments
-
SN65LVDS93DGGR
Texas Instruments
-
TDES954RGZT
Texas Instruments
-
SN65LV1224BRHBT
Texas Instruments
-
DS90UB914QSQE/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
