Texas Instruments DS90UR906QSQE/NOPB
- Part No.:
- DS90UR906QSQE/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 60-WFQFN Exposed Pad
- Datasheet:
-
DS90UR906QSQE/NOPB.pdf
- Description:
- IC DESERIALIZER 1.82GBPS 60WQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
DS90UR906QSQE/NOPB from Texas Instruments is a 60-pin WQFN automotive-grade FPD-Link II deserializer that recovers RGB888 video, HS/VS/DE control signals, and pixel clock from a single AC-coupled STP pair at 5–65 MHz PCLK (140 Mbps–1.82 Gbps). It operates without reference clock or training sequence, delivers real-time LOCK status, and supports 1.8-V/3.3-V LVCMOS I/O for automotive display interconnects.
For engineers reviewing the DS90UR906QSQE/NOPB datasheet, DS90UR906QSQE/NOPB pinout, DS90UR906QSQE/NOPB application, or DS90UR906QSQE/NOPB equivalent, key selection criteria include lock-detection reliability, receiver equalization adjustability, spread-spectrum clocking (SSCG) support, output slew control (OS_PCLK/OS_DATA), and AEC-Q100 Grade 2 qualification for navigation and infotainment displays.
Technical Context
The DS90UR906QSQE/NOPB implements a fully autonomous clock-data recovery (CDR) architecture with no external reference clock required. Its integrated receiver equalization (EQ[3:0] strap-selectable up to 24 dB) compensates for channel loss in up to 10-meter STP cables, while the LOCK pin provides deterministic real-time link status reporting independent of register reads.
It supports backward compatibility with legacy serializers via CONFIG[1:0] strapping and enables EMI reduction through optional SSCG (SSC[3:0]-configurable range) and output slew control (OS_PCLK/OS_DATA). The deserializer outputs parallel RGB888 + HS/VS/DE/PCLK with configurable strobe edge (RFB strap) and power-down behavior governed by OSS_SEL and OP_LOW straps.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| PCLK Range | 5–65 MHz - supports QVGA to XGA resolution with 24-bit color depth at full bandwidth |
| Data Rate | 140 Mbps to 1.82 Gbps - enables high-fidelity video transport over single-pair AC-coupled STP cable |
| Operating Temp | –40°C to +105°C - AEC-Q100 Grade 2 qualified for under-hood and dashboard automotive environments |
| I/O Voltage | 1.8 V or 3.3 V - dual-supply LVCMOS interface simplifies integration with diverse graphics processors |
| ESD Rating | >8-kV HBM, ISO 10605 - robust protection for automotive assembly and field operation |
| Package | 60-pin WQFN (9.0 mm × 9.0 mm) - thermally enhanced layout with exposed DAP for PCB heat dissipation |
| Power Down | PDB-controlled - reduces IDD to minimal state; output states configurable via OSS_SEL/OP_LOW straps |
Pinout & Package
DS90UR906QSQE/NOPB uses a 60-pin WQFN package (9.0 mm × 9.0 mm) with exposed thermal pad (DAP = GND) requiring ≥9 vias to ground plane. Pin functions are defined at power-up via strap pins; LVCMOS I/O supports 1.8-V/3.3-V logic levels.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| R[7:0], G[7:0], B[7:0] | Parallel RGB data outputs | Tri-state capable; output state in power-down controlled by OSS_SEL strap per Table 6 |
| HS, VS, DE, PCLK | Video timing signal outputs | Strobe edge selectable via RFB strap; pulse width constraints enforced per CONFIG[1:0] setting |
| LOCK | Real-time PLL lock indicator | Active-HIGH when CDR locked; used for system readiness signaling without register polling |
| PDB | Power-down enable input | Active-LOW disables deserializer; triggers reset of control registers and configures output sleep state |
| CONFIG[1:0] | Serializer compatibility mode select | Strap-selectable interface to DS90UR905Q-Q1 (00/01), DS90UR241 (10), or DS90C241 (11) |
| RIN+, RIN− | FPD-Link II differential inputs | AC-coupled (100 nF); require external termination; support up to 10 m STP cable with EQ[3:0] adjustment |
| SCL / SDA | I²C-compatible configuration bus | Open-drain; require external pullups to VDDIO; used for runtime register access and diagnostics |
| CMF | Common-mode filter input | AC-coupled to ground (≥100 nF) to improve noise immunity on differential receiver inputs |
Key Features
| Feature | Design Value |
|---|---|
| Autonomous CDR | Locks to serial stream without reference clock or training pattern - eliminates timing dependency on host processor |
| Adjustable Receiver EQ | Four-level strap-selectable equalization (0–24 dB) - adapts to varying cable lengths and losses up to 10 meters |
| Real-Time LOCK Reporting | Dedicated open-drain output pin - enables hardware-triggered system initialization without software polling |
| Configurable Output Slew | Separate OS_PCLK and OS_DATA straps - independently tune PCLK and data edge rates to meet EMI and signal integrity targets |
| Spread Spectrum Clocking (SSCG) | Strap-configurable frequency modulation (SSC[3:0]) - reduces peak EMI emissions on parallel RGB bus |
| Backward Compatibility | CONFIG[1:0] strapping supports interoperability with DS90UR905Q-Q1, DS90UR241, and DS90C241 serializers |
Applications
| Automotive Navigation Display | Automotive Infotainment Display |
|---|---|
Use Scenario: High-resolution map rendering and turn-by-turn guidance in instrument cluster or center console. IC Role / Device Role / Timing Role: Deserializes video from central graphics processor to remote LCD panel over compact STP harness. Use Value: Eliminates skew between RGB data and timing signals, enabling stable QVGA–XGA display at 65 MHz PCLK with <10 ns inter-pair skew. | Use Scenario: Video playback, media UI, and rear-seat entertainment in multi-display vehicle architectures. IC Role / Device Role / Timing Role: Receives serialized video stream and reconstructs synchronized RGB888 + HS/VS/DE/PCLK for TFT-LCD driving. Use Value: Supports 24-bit color depth and real-time LOCK feedback for fail-safe display activation during vehicle startup sequences. |
| ADAS Camera Interface | Digital Rearview Mirror |
Use Scenario: Transmitting high-frame-rate camera feed from front/side/rear sensors to domain controller. IC Role / Device Role / Timing Role: Deserializes low-latency video over extended STP cable with deterministic lock acquisition. Use Value: Achieves sub-millisecond lock time and maintains link integrity across temperature extremes (–40°C to +105°C). | Use Scenario: Replacing analog mirror with digital display fed by wide-angle camera module. IC Role / Device Role / Timing Role: Converts serialized camera output into parallel RGB interface compatible with display timing controller. Use Value: Enables EMI-optimized cabling in constrained cabin space while meeting AEC-Q100 Grade 2 reliability requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPD-Link II deserializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90UR906QSQ/NOPB | No suffix indicates non-automotive grade; lacks AEC-Q100 qualification and extended temp range | Restricted to industrial/commercial displays; not suitable for safety-critical automotive use | Select DS90UR906QSQE/NOPB for automotive deployments requiring Grade 2 qualification and production traceability |
| DS90UR907QSQE/NOPB | Includes integrated HDCP engine and MIPI DSI output; higher pin count (64-pin WQFN) | Targets premium infotainment with content protection and mobile display interfaces | Choose DS90UR906QSQE/NOPB when cost-sensitive, non-HDCP automotive displays need proven FPD-Link II interoperability |
Compared with DS90UR906QSQ/NOPB, the DS90UR906QSQE/NOPB adds AEC-Q100 Grade 2 validation and extended temperature support; versus DS90UR907QSQE/NOPB, it omits HDCP and MIPI DSI but reduces BOM cost and simplifies layout for standard RGB-TTL displays.
Availability
DS90UR906QSQE/NOPB is available at Aetrix Electronics and suitable for automotive navigation systems, infotainment head units, and ADAS camera interfaces requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for DS90UR906QSQE/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies with deep expertise in automotive electronics and high-speed interface solutions.
The DS90UR906QSQE/NOPB belongs to TI's FPD-Link II serializer/deserializer product line, designed specifically for robust, low-skew, high-bandwidth video transport in automotive display systems.
FAQ
What is the primary function of the DS90UR906QSQE/NOPB in an automotive display system?
The DS90UR906QSQE/NOPB serves as the deserializer in an FPD-Link II interface, recovering RGB888 video data and HS/VS/DE/PCLK timing signals from a single AC-coupled differential pair. It enables high-fidelity video transmission from a graphics processor to a remote LCD panel while eliminating clock-data skew and reducing connector size and weight - a core requirement for automotive navigation and infotainment displays.
Does the DS90UR906QSQE/NOPB require an external reference clock to operate?
No, the DS90UR906QSQE/NOPB does not require an external reference clock. Its integrated clock-data recovery (CDR) circuit locks directly to the incoming FPD-Link II serial stream without training sequences or SYNC patterns. This autonomous operation is confirmed in the datasheet Section 3 and functional block diagram, making DS90UR906QSQE/NOPB suitable for systems where clock distribution complexity must be minimized.
How is link status monitored on the DS90UR906QSQE/NOPB?
Link status is monitored via the dedicated LOCK pin on the DS90UR906QSQE/NOPB. When LOCK = HIGH, the internal PLL is locked and parallel outputs are valid; when LOCK = LOW, the CDR is unlocked and outputs are held in a defined state per OSS_SEL configuration. This real-time hardware flag eliminates the need for register polling and is explicitly documented in the Pin Functions table (Pin 32) and Section 8.3 of the datasheet.
Can the DS90UR906QSQE/NOPB interface with older FPD-Link I devices?
No, the DS90UR906QSQE/NOPB is not compatible with FPD-Link I devices. It is designed exclusively for FPD-Link II (LVDS-based, AC-coupled, scrambled) protocols. However, it supports backward compatibility with earlier FPD-Link II serializers like DS90UR241 and DS90C241 via CONFIG[1:0] strap settings - a capability clearly specified in the Deserializer Pin Functions table and Section 8.4 of the datasheet.
What are the power supply requirements for the DS90UR906QSQE/NOPB?
The DS90UR906QSQE/NOPB requires six distinct supply rails: VDDIO (1.8 V or 3.3 V ± tolerance), VDDL (1.8 V), VDDPR (1.8 V), VDDCMLO (1.8 V), VDDR (1.8 V), and VDDSC (1.8 V). All 1.8-V supplies must be within ±5%; VDDIO accepts either 1.8 V ±5% or 3.3 V ±10%. Power sequencing is critical - VDD ramps must be faster than 1.5 ms monotonic rise, or a capacitor on PDB is required per Section 10.1 of the datasheet.
DS90UR906QSQE/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 60-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Deserializer
- Data Rate:
- 1.82Gbps
- Input Type:
- FPD-Link II, LVDS
- Output Type:
- LVCMOS
- Number of Inputs:
- 1
- Number of Outputs:
- 24
- Voltage - Supply:
- 1.71V ~ 1.89V, 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 60-WQFN (9x9)
DS90UR906QSQE/NOPB FAQ
1.How can I place an order for DS90UR906QSQE/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90UR906QSQE/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90UR906QSQE/NOPB reliable?
The price and inventory of DS90UR906QSQE/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90UR906QSQE/NOPB is usually 5 days.
3.What payment methods are accepted for DS90UR906QSQE/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90UR906QSQE/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90UR906QSQE/NOPB?
DS90UR906QSQE/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90UR906QSQE/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90UR906QSQE/NOPB?
For technical support, including DS90UR906QSQE/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90UR906QSQE/NOPB requirements.
6.How does Aetrix verify that DS90UR906QSQE/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90UR906QSQE/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90UR906QSQE/NOPB meets industry standards.
7.What is the process for return or replacement of DS90UR906QSQE/NOPB?
All DS90UR906QSQE/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90UR906QSQE/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90UR906QSQE/NOPB part is unused and in its original packaging.
Return procedure for DS90UR906QSQE/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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