Texas Instruments DS90UR908QSQ/NOPB
- Part No.:
- DS90UR908QSQ/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
DS90UR908QSQ/NOPB.pdf
- Description:
- IC DESERIALIZER 65MHZ 48WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,075
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS90UR908QSQ/NOPB from Texas Instruments is an automotive-grade FPD-Link II to FPD-Link converter IC that deserializes 24-bit RGB888 video + HS/VS/DE control signals from a single AC-coupled LVDS pair into five LVDS outputs (four data lanes + one clock lane), operating across 5–65 MHz pixel clocks (140 Mbps–1.82 Gbps line rate) with no reference clock required.
For engineers reviewing the DS90UR908QSQ/NOPB datasheet, DS90UR908QSQ/NOPB pinout, DS90UR908QSQ/NOPB application, or DS90UR908QSQ/NOPB equivalent, key selection considerations include its AEC-Q100 Grade 2 qualification, integrated input equalization for 10-meter STP cable support, LVDS output voltage select (±250 mV / ±400 mV), real-time LOCK status reporting, and backward compatibility with DS90C241/DS90UR241/DS99R421 serializers.
Technical Context
The DS90UR908QSQ/NOPB implements a DC-balanced decoding architecture to enable AC-coupled interconnects and employs embedded clock recovery without training sequences or external reference clocks. Its PLL achieves fast random-data lock in ≤8 ms at 65 MHz with SSCG-enabled jitter tolerance >0.5 UI.
It supports configurable mapping (LSB/MSB on TxOUT3), programmable spread-spectrum clocking (±0.5% to ±2% deviation, 8–100 kHz modulation), and optional I²C-compatible serial control for register-level configuration of CONFIG[1:0], MAPSEL, VODSEL, and LFMODE - all while maintaining pin-strapped operation for standalone deployment.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Interface | Single-pair FPD-Link II LVDS (AC-coupled, internal 100 Ω termination) |
| Output Interface | 5-channel FPD-Link LVDS: TxOUT[3:0]± + TxCLKOUT± (4 data + 1 clock) |
| Pixel Clock Range | 5–65 MHz - enables QVGA to XGA displays with RGB888 color depth |
| Data Rate | 140 Mbps to 1.82 Gbps - supports up to 24-bit color + HS/VS/DE + 3 low-speed bits |
| Supply Voltages | VDDA/VDDL/VDDP/VDDSC = 1.8 V ±5%; VDDTX = 3.3 V ±10%; VDDIO = 1.8 V or 3.3 V |
| Power Dissipation | 135 mA total typical (95 mA analog + 40 mA FPD-Link + 0.8 mA I/O) at 65 MHz, 1.89 V/3.6 V |
| Operating Temp | −40°C to +105°C - qualified per AEC-Q100 Grade 2 for automotive display systems |
Pinout & Package
DS90UR908QSQ/NOPB is housed in a thermally enhanced 48-pin WQFN package (7 mm × 7 mm, 0.5 mm pitch) with exposed DAP grounded to PCB ground plane via ≥9 vias. Pin functions are validated per TI SNLS317H datasheet Rev. April 2013.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RIN+, RIN− | FPD-Link II differential input | AC-coupled LVDS receiver pair with internal 100 Ω termination; supports up to 10 m STP cable |
| TxOUT[3:0]±, TxCLKOUT± | FPD-Link LVDS outputs | Four true/inverting data lanes + clock pair; VOD selectable ±250 mV or ±400 mV for EMI optimization |
| LOCK | Real-time link status indicator | LVCMOS output: HIGH = PLL locked and valid video data; used for system sync or fault detection |
| PDB | Power-down control input | Active-HIGH enable; pulls all LVDS outputs to TRI-STATE and reduces supply current to ≤2 mA |
| CONFIG[1:0] | Backward compatibility mode select | Configures interface to DS90UR907Q/DS90UR905Q (default), DS90UR241/DS99R421, or DS90C241 |
| VODSEL | LVDS output voltage select | Pin-strapped control of differential swing: 500 mVp-p (low EMI) or 900 mVp-p (noise margin) |
| MAPSEL | Color bit mapping control | Selects LSB-first or MSB-first routing of RGB888 data across TxOUT[3:0] lanes |
| SSC[2:0] | Spread-spectrum clocking control | 3-bit select for ±0.5%/±1%/±2% frequency deviation and 8/33/100 kHz modulation |
Key Features
| Feature | Design Value |
|---|---|
| Reference-clock-free lock | Acquires lock to random FPD-Link II data without training patterns or external clock - simplifies timing design |
| Adjustable input equalization | EQ pin enables ~13 dB gain to compensate for cable loss up to 10 meters, improving signal integrity |
| Real-time link monitoring | LOCK pin provides immediate hardware indication of PLL lock state for system diagnostics and fail-safe response |
| Configurable LVDS output swing | VODSEL selects ±250 mV or ±400 mV differential output voltage to balance noise immunity vs. EMI reduction |
| Backward compatibility modes | CONFIG[1:0] pins support interoperability with three legacy FPD-Link II serializer generations |
| Integrated BIST support | BISTEN/PASS pins enable hardware-level link integrity testing without host processor involvement |
Applications
| Automotive Navigation Display | Automotive Infotainment Display |
|---|---|
|
Use Scenario: High-resolution TFT-LCD cluster display receiving video from graphics processor over long cable harnesses in vehicle cabin. IC Role / Device Role / Timing Role: FPD-Link II deserializer converting serialized video stream to parallel LVDS for display timing controller. Use Value: Enables compact 2-wire interconnect (vs. 25+ parallel lines), eliminates skew management, and maintains <1.82 Gbps throughput over 10 m STP cable. |
Use Scenario: Central infotainment head unit driving dual-zone rear-seat entertainment displays. IC Role / Device Role / Timing Role: Video interface bridge supporting RGB888 + HS/VS/DE with configurable bit mapping for diverse panel vendors. Use Value: MAPSEL and CONFIG[1:0] pins allow single BOM to support multiple display modules without firmware changes. |
| Instrument Cluster Video Interface | Digital Rearview Mirror System |
|
Use Scenario: Safety-critical digital instrument cluster requiring AEC-Q100-compliant video path with deterministic latency. IC Role / Device Role / Timing Role: Low-latency deserializer with tDD ≤10*T (T = pixel clock period) and real-time LOCK feedback for fault detection. Use Value: Meets ASIL-B timing requirements via guaranteed lock time ≤8 ms and power-down delay <12 ns. |
Use Scenario: Camera-to-mirror video link in rearview mirror assembly with strict EMI limits in cabin environment. IC Role / Device Role / Timing Role: EMI-reduced FPD-Link transmitter using SSCG and low-swing LVDS outputs. Use Value: Spread-spectrum clocking (±2%, 100 kHz) and selectable 500 mVp-p output reduce peak radiated emissions by >10 dB. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPD-Link II deserializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS90UR907Q | Serializer companion; not functionally equivalent - transmits FPD-Link II, does not receive | Used on source side (GPU/SoC); requires paired DS90UR908Q on display side | Select DS90UR907Q only when building full FPD-Link II link; not a drop-in replacement |
| DS90C241 | Legacy FPD-Link I serializer; lacks FPD-Link II features (DC balancing, embedded clock, equalization) | Supports only 24-bit RGB at ≤35 MHz; no backward compatibility with DS90UR908Q's CONFIG modes | DS90UR908Q operates in GEN1 mode with DS90C241 but cannot replace it - different functional role |
Compared with DS90UR908QSQ/NOPB, DS90UR907Q serves the complementary transmit function in the same chipset, while DS90C241 is an obsolete serializer incompatible as a direct alternative - DS90UR908QSQ/NOPB has no pin-compatible or functional drop-in substitute due to its unique FPD-Link II deserialization architecture and AEC-Q100 qualification.
Availability
DS90UR908QSQ/NOPB is available at Aetrix Electronics and suitable for automotive navigation, infotainment, and digital instrument cluster applications requiring stable component supply, AEC-Q100 compliance, and long-term production continuity.
Supply support for DS90UR908QSQ/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity solutions, with deep expertise in automotive electronics and high-speed interface IP.
The DS90UR908QSQ/NOPB belongs to TI's FPD-Link II serializer/deserializer product line, designed specifically for robust, low-EMI, high-bandwidth video transmission in automotive cockpit displays and ADAS subsystems.
FAQ
What is the primary function of the DS90UR908QSQ/NOPB in an automotive display system?
The DS90UR908QSQ/NOPB functions as an FPD-Link II deserializer that converts a high-speed, single-pair serialized video stream (with embedded clock and RGB888 + HS/VS/DE signals) into a standard 5-channel FPD-Link LVDS interface for display timing controllers. It operates without a reference clock, supports 5–65 MHz pixel rates, and is AEC-Q100 Grade 2 qualified for under-hood and cabin display applications.
Does the DS90UR908QSQ/NOPB require an external reference clock to achieve lock?
No, the DS90UR908QSQ/NOPB does not require an external reference clock. It uses embedded clock recovery to lock directly to the incoming FPD-Link II serial stream - even with random data patterns - achieving lock in ≤8 ms at 65 MHz. This eliminates clock distribution complexity and improves system robustness in automotive environments where reference clock routing is challenging.
How does the DS90UR908QSQ/NOPB support long-cable interconnects up to 10 meters?
The DS90UR908QSQ/NOPB supports 10-meter STP cables via integrated input equalization (enabled by EQ pin), internal 100 Ω LVDS termination, and AC-coupling compatibility. Its adjustable equalizer gain (~13 dB) compensates for high-frequency loss in long cables, while DC-balanced encoding preserves signal integrity across capacitive coupling points - all validated per TI SNLS317H datasheet.
What are the key differences between DS90UR908QSQ/NOPB and DS90C241?
DS90UR908QSQ/NOPB is an FPD-Link II deserializer supporting 5–65 MHz, embedded clock recovery, DC balancing, and adjustable equalization; DS90C241 is an older FPD-Link I serializer limited to ≤35 MHz with no embedded clock or equalization. They serve opposite roles (receive vs. transmit) and are not interchangeable - DS90UR908QSQ/NOPB can interface with DS90C241 only in backward-compatibility mode, not as a replacement.
Can the DS90UR908QSQ/NOPB be configured via software or only through hardware pins?
The DS90UR908QSQ/NOPB supports both hardware pin-strapping and software configuration. Critical settings like CONFIG[1:0], MAPSEL, VODSEL, and SSC[2:0] can be set at power-up via LVCMOS inputs, while optional I²C-compatible serial control (SCL/SDA pins) allows dynamic register-level reconfiguration of these and additional parameters - enabling flexible system integration without hardware changes.
DS90UR908QSQ/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Deserializer
- Data Rate:
- 1.82Gbps
- Input Type:
- FPD-Link II, LVDS
- Output Type:
- FPD-Link, LVDS
- Number of Inputs:
- 1
- Number of Outputs:
- 5
- Voltage - Supply:
- 1.71V ~ 1.89V, 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-WQFN (7x7)
DS90UR908QSQ/NOPB FAQ
1.How can I place an order for DS90UR908QSQ/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS90UR908QSQ/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS90UR908QSQ/NOPB reliable?
The price and inventory of DS90UR908QSQ/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS90UR908QSQ/NOPB is usually 5 days.
3.What payment methods are accepted for DS90UR908QSQ/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS90UR908QSQ/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS90UR908QSQ/NOPB?
DS90UR908QSQ/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS90UR908QSQ/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS90UR908QSQ/NOPB?
For technical support, including DS90UR908QSQ/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS90UR908QSQ/NOPB requirements.
6.How does Aetrix verify that DS90UR908QSQ/NOPB is sourced from the original manufacturer or authorized distributors?
All DS90UR908QSQ/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS90UR908QSQ/NOPB meets industry standards.
7.What is the process for return or replacement of DS90UR908QSQ/NOPB?
All DS90UR908QSQ/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS90UR908QSQ/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS90UR908QSQ/NOPB part is unused and in its original packaging.
Return procedure for DS90UR908QSQ/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS90UR908QSQ/NOPB Tags

-
SN65HVS880PWPR
Texas Instruments

-
SN65HVS882PWPR
Texas Instruments

-
FIN3386MTDX
onsemi

-
FIN3385MTDX
onsemi

-
SN65LV1023ARHBR
Texas Instruments

-
SN65LV1023ADBR
Texas Instruments

-
SN65LV1224BDBR
Texas Instruments

-
SN65LVDS93ADGGR
Texas Instruments

-
SN65LVDS93DGGR
Texas Instruments

-
TDES954RGZT
Texas Instruments

-
SN65LV1224BRHBT
Texas Instruments

-
DS90UB914QSQE/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

