Texas Instruments DS92LV16TVHG/NOPB

Overview

DS92LV16TVHG/NOPB from Texas Instruments is a monolithic 16-bit parallel-to-serial/serial-to-parallel Bus LVDS SERDES IC supporting 25–80 MHz clock rates, delivering 2.56 Gbps full-duplex throughput with embedded clock recovery, ±100 mV receiver input threshold, and operation across −40°C to +85°C for backplane and cable interconnects in industrial imaging systems.

For engineers reviewing the DS92LV16TVHG/NOPB datasheet, DS92LV16TVHG/NOPB pinout, DS92LV16TVHG/NOPB application, or DS92LV16TVHG/NOPB equivalent, key selection considerations include BLVDS serial link integrity, independent TX/RX power-down control, line/local loopback test capability, hot-plug synchronization behavior, and compatibility with 3.3 V LVCMOS/LVTTL parallel buses.

Technical Context

The DS92LV16TVHG/NOPB integrates a serializer and deserializer on one die with separate PLLs: the serializer locks to TCLK (25–80 MHz), while the deserializer locks to REFCLK or recovers clock from the BLVDS stream. It supports three operational states-Initialization, Data Transfer, and Resynchronization-and two passive states-Powerdown and TRI-STATE.

It implements 16:1 serialization with start/stop framing bits (18-bit serial word), enabling 16-bit payload at 16×TCLK rate (e.g., 1.28 Gbps at 80 MHz). Clock recovery uses deterministic jitter tolerance up to 140 ps (80 MHz) and noise margins of ±230 ps (80 MHz), with loss-of-lock detection reported via the LOCK pin.

Key Specifications

Pinout & Package

DS92LV16TVHG/NOPB is housed in an 80-pin LQFP package (12 mm × 12 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are validated per TI SNLS138H datasheet Figures 1, 7, 8, 12, and 13.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar SERDES applications.

Compared with DS92LV010ATM/NOPB, DS92LV16TVHG/NOPB provides full 16-bit width and built-in diagnostics; compared with MAX9205+MAX9206, it reduces component count, power sequencing complexity, and inter-chip timing uncertainty-making it optimal for space-constrained, single-link industrial backplanes.

Availability

DS92LV16TVHG/NOPB is available at Aetrix Electronics and suitable for industrial imaging backplanes, avionics data concentrators, automated test equipment, and robotic vision interfaces requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for DS92LV16TVHG/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface ICs and industrial-grade reliability.

The DS92LV16TVHG/NOPB belongs to TI's Bus LVDS SERDES product line, engineered specifically for noise-immune, low-skew parallel-to-serial bridging in industrial, medical, and aerospace backplane and cable interconnect applications.

FAQ

What is the maximum supported clock rate for DS92LV16TVHG/NOPB?

The DS92LV16TVHG/NOPB supports a maximum clock rate of 80 MHz on both TCLK and REFCLK inputs. At this rate, it achieves a 16-bit payload throughput of 1.28 Gbps and full-duplex serial throughput of 2.56 Gbps. Operation above 80 MHz is not characterized or guaranteed per the SNLS138H datasheet.

Does DS92LV16TVHG/NOPB require external PLL components?

No, DS92LV16TVHG/NOPB integrates fully self-contained PLLs for both serializer and deserializer blocks. The device operates with only a single +3.3 V supply and does not require external crystals, loop filters, or frequency-setting resistors-reducing bill-of-materials cost and layout footprint.

How does DS92LV16TVHG/NOPB handle loss of clock lock during operation?

When DS92LV16TVHG/NOPB loses PLL lock-detected after two consecutive missing clock edges-the LOCK pin goes high, and ROUT outputs become invalid. The deserializer automatically enters resynchronization mode, attempting to reacquire lock either from random data or upon receipt of a new SYNC pattern, with lock times ranging from 0.9 μs to 10 μs depending on mode and frequency.

Can DS92LV16TVHG/NOPB operate with different clock sources for transmit and receive?

Yes, DS92LV16TVHG/NOPB supports independent clock domains: TCLK drives the serializer, while REFCLK drives the deserializer's initial PLL lock. Once locked to the serial stream, the deserializer recovers clock embedded in the BLVDS data-enabling asynchronous operation between source and sink clocks, provided they fall within ±5% frequency tolerance.

What package type and thermal characteristics does DS92LV16TVHG/NOPB use?

DS92LV16TVHG/NOPB uses an 80-pin LQFP package (12 mm × 12 mm, 0.5 mm pitch) with exposed thermal pad. Its thermal resistance is θJA = 43°C/W and θJC = 11.1°C/W, supporting operation up to +85°C ambient with standard PCB copper pour and two-via connections per power pin.