Texas Instruments DS92LX2122SQ/NOPB
- Part No.:
- DS92LX2122SQ/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Serializers, Deserializers
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
DS92LX2122SQ/NOPB.pdf
- Description:
- IC DESERIALIZER BI-DIR 48WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,156
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
DS92LX2122SQ/NOPB from Texas Instruments is a Channel Link III deserializer IC that converts high-speed serial data from a DS92LX2121 serializer into 21-bit parallel LVCMOS video and control signals (RGB666 + HS/VS/DE), supports 10–50 MHz pixel clocks, embeds DC-balanced coding for AC-coupled interconnects up to 10 meters, and integrates programmable receive equalization for loss compensation. It operates across −40°C to +85°C with 1.8V core and I/O supply options.
For engineers reviewing the DS92LX2122SQ/NOPB datasheet, DS92LX2122SQ/NOPB pinout, DS92LX2122SQ/NOPB application, or DS92LX2122SQ/NOPB equivalent, key selection criteria include its bi-directional I²C control channel, LOCK status reporting, receiver output drive strength control, staggered outputs for EMI reduction, and support for both 1.8V and 3.3V parallel interfaces.
Technical Context
The DS92LX2122SQ/NOPB implements a CDR-based deserialization architecture with embedded clock recovery, eliminating the need for a separate reference clock at the receiver. It decodes DC-balanced Channel Link III streams carrying 21-bit parallel data plus 3-bit control, and reconstructs synchronous PCLK-aligned outputs with configurable edge alignment via RFB register.
Its bi-directional back channel uses the same differential pair for full-duplex I²C-compatible control traffic, supporting master/slave mode selection and single-pin ID addressing via CAD resistor divider. Integrated features include AT-speed BIST with PASS/LOCK monitoring, programmable spread-spectrum clocking (SSCG), and receiver output drive strength control (RDS) for signal integrity tuning.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data throughput | Up to 1050 Mbits/sec - enables transmission of 18-bit color (RGB666) + sync signals at 50 MHz PCLK over single differential pair |
| Input clock range | 10 MHz to 50 MHz - supports standard display timing including VGA, SVGA, and XGA resolutions |
| Parallel interface | 21-bit LVCMOS outputs (ROUT[20:0]) - delivers RGB666 + HS/VS/DE with 1.8V/3.3V I/O compatibility |
| Power supply | Single 1.8V core (VDDD/VDDPLL/VDDCML/VDDR/VDDSSCG) - reduces board-level power conversion complexity |
| ESD rating | ≥±25 kV air discharge on CML pins - ensures robustness in industrial cable-connected display systems |
| Operating temperature | −40°C to +85°C - qualified for extended-temperature industrial and medical imaging environments |
| Equalization | Programmable receive equalization - compensates for up to 10-meter shielded twisted-pair channel loss |
Pinout & Package
DS92LX2122SQ/NOPB is housed in a 48-pin WQFN package (RHS footprint, 7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad (DAP) requiring ≥16 vias to ground plane.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ROUT[20:0] | LVCMOS parallel data outputs | Deliver reconstructed RGB666 + HS/VS/DE signals; individually configurable for 1.8V/3.3V operation |
| PCLK | Pixel clock output | Synchronous clock aligned to parallel data; edge polarity set by RFB register configuration |
| GPI[3:0] | General-purpose inputs | Configurable digital inputs for system status feedback or external event detection |
| RIN+, RIN− | CML differential serial input | AC-coupled (0.1 µF) high-speed forward channel input; integrated 100 Ω termination |
| SCL, SDA | I²C bidirectional control bus | Open-drain interface for device configuration and link monitoring; requires external pull-ups |
| LOCK | PLL lock status indicator | Active-high signal confirming stable CDR lock; used for system readiness validation |
| PDB | Power-down control input | Active-high enables sleep mode: tri-states outputs, shuts down PLL, minimizes IDD to <125 µA |
| BISTEN, PASS | AT-speed BIST control/status | Enables built-in self-test; PASS output asserts high on error-free link validation |
Key Features
| Feature | Design Value |
|---|---|
| Embedded clock recovery | Eliminates need for separate reference clock at display end, simplifying cabling and reducing skew sensitivity |
| DC-balanced encoding | Enables reliable AC-coupling over long cables (up to 10 m) without baseline wander or DC drift |
| Programmable receive equalization | Compensates frequency-dependent loss in shielded twisted-pair media, maintaining signal integrity |
| Staggered output drivers | Reduces simultaneous switching noise (SSN) and EMI emissions during parallel data transitions |
| Integrated SSCG | Reduces electromagnetic interference through controlled clock spectrum spreading (±0.5% to ±2.0% deviation) |
| 1.8V/3.3V I/O compatibility | Supports direct interfacing with diverse timing controllers and FPGAs without level-shifting circuitry |
Applications
| Industrial Touch Displays | Medical Imaging Monitors |
|---|---|
Use Scenario: High-reliability video transmission from graphics controller to ruggedized touch panel in factory HMIs. IC Role / Device Role / Timing Role: Deserializes Channel Link III stream into RGB666 + HS/VS/DE for display timing controller; provides LOCK status for system boot validation. Use Value: Enables single-cable 10-meter video+control routing with ESD-hardened CML I/O and −40°C to +85°C operation. | Use Scenario: Real-time diagnostic image delivery from imaging processor to high-resolution clinical display. IC Role / Device Role / Timing Role: Receives serialized video with embedded clock; reconstructs jitter-controlled PCLK and parallel data for frame buffer interface. Use Value: Delivers deterministic latency (<12 ns typical deserializer delay) and AT-speed BIST for safety-critical link integrity verification. |
| Automotive Digital Instrument Clusters | Avionics Display Interfaces |
Use Scenario: Video transport from central domain controller to TFT cluster display in harsh automotive environments. IC Role / Device Role / Timing Role: Converts serializer output to parallel RGB interface while providing programmable RDS for impedance matching to display PCB traces. Use Value: Supports 50 MHz PCLK for 1280×720 resolution with spread-spectrum clocking to meet CISPR-25 Class 5 EMC requirements. | Use Scenario: Secure, low-latency video distribution between flight management computer and multifunction displays. IC Role / Device Role / Timing Role: Acts as trusted deserialization endpoint with LOCK and PASS outputs for DO-254-compliant health monitoring. Use Value: Provides dual-voltage I/O (1.8V/3.3V), IEC 61000-4-2 ESD compliance, and BIST-enforced link validation per avionics safety protocols. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar deserializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DS92LV2422SQ/NOPB | Lower data rate (up to 660 Mbps); supports only 16-bit RGB + sync; no integrated SSCG or BIST | Targeted for cost-sensitive VGA-only displays without advanced diagnostics or EMI mitigation | Select when bandwidth ≤660 Mbps suffices and BIST/SSCG are unnecessary |
| SN65LVDS302RTJT | Non-Channel Link chipset; requires external clock; no embedded control channel or equalization | Suitable for point-to-point LVDS links with separate clock routing and shorter distances (<3 m) | Choose only if system already uses discrete clock distribution and does not require bi-directional control |
Compared with DS92LV2422SQ/NOPB and SN65LVDS302RTJT, DS92LX2122SQ/NOPB uniquely combines 1050 Mbps throughput, integrated I²C back channel, programmable equalization, and production-ready BIST-making it the only option for high-fidelity, long-cable, safety-monitored display links requiring minimal PCB routing overhead.
Availability
DS92LX2122SQ/NOPB is available at Aetrix Electronics and suitable for industrial touch displays, medical imaging monitors, and automotive digital instrument clusters requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for DS92LX2122SQ/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with broad industrial and automotive qualification expertise.
The DS92LX2122SQ/NOPB belongs to TI's Channel Link III chipset family, engineered specifically for high-reliability, long-cable video transport in displays where EMI resilience, link diagnostics, and single-cable integration are critical design requirements.
FAQ
What is the maximum supported cable length for DS92LX2122SQ/NOPB?
The DS92LX2122SQ/NOPB supports up to 10 meters of shielded twisted-pair cable when paired with the DS92LX2121 serializer, enabled by its programmable receive equalization and DC-balanced Channel Link III encoding. Performance depends on cable quality and frequency; at 50 MHz PCLK, verified operation is confirmed to 10 m with standard STP. The DS92LX2122SQ/NOPB datasheet specifies equalization settings optimized for this reach.
Does DS92LX2122SQ/NOPB require an external reference clock?
No, DS92LX2122SQ/NOPB does not require an external reference clock. It uses embedded clock recovery (CDR) to extract timing directly from the incoming Channel Link III serial stream. This eliminates clock skew concerns and simplifies system design by removing the need for a separate clock line or oscillator at the display end. The DS92LX2122SQ/NOPB LOCK pin confirms successful CDR lock.
How does the bi-directional control channel work on DS92LX2122SQ/NOPB?
The DS92LX2122SQ/NOPB implements a full-duplex I²C-compatible control channel over the same differential pair used for high-speed data, enabling real-time configuration and status exchange without additional wires. It supports master/slave mode selection via the M/S pin and device addressing via the CAD pin. The DS92LX2122SQ/NOPB uses open-drain SCL/SDA pins requiring external pull-up resistors to VDDIO.
Can DS92LX2122SQ/NOPB operate with both 1.8V and 3.3V I/O voltages?
Yes, DS92LX2122SQ/NOPB supports 1.8V or 3.3V LVCMOS I/O on its parallel interface (ROUT[20:0], PCLK, GPI[3:0]), configured independently per supply rail (VDDIO). Core analog and digital supplies (VDDD, VDDPLL, etc.) remain fixed at 1.8V. This dual-voltage capability allows direct interfacing with legacy 3.3V timing controllers or modern 1.8V FPGAs without external level shifters. The DS92LX2122SQ/NOPB electrical characteristics table specifies both voltage modes.
What is the purpose of the PASS and LOCK pins on DS92LX2122SQ/NOPB?
The LOCK pin indicates CDR lock status (high = locked), essential for system boot sequencing and link readiness. The PASS pin reports AT-speed BIST result (high = error-free transmission), enabling runtime link integrity validation without interrupting video flow. Both are LVCMOS outputs used for hardware-level fault detection and diagnostics. In DS92LX2122SQ/NOPB systems, these pins feed directly into host microcontroller GPIOs for autonomous health monitoring.
DS92LX2122SQ/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Deserializer
- Data Rate:
- 1.05Gbps
- Input Type:
- Channel Link III (CML)
- Output Type:
- Channel Link III (LVCMOS)
- Number of Inputs:
- 1
- Number of Outputs:
- 21
- Voltage - Supply:
- 1.71V ~ 1.89V, 3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-WQFN (7x7)
DS92LX2122SQ/NOPB FAQ
1.How can I place an order for DS92LX2122SQ/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for DS92LX2122SQ/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for DS92LX2122SQ/NOPB reliable?
The price and inventory of DS92LX2122SQ/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for DS92LX2122SQ/NOPB is usually 5 days.
3.What payment methods are accepted for DS92LX2122SQ/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for DS92LX2122SQ/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for DS92LX2122SQ/NOPB?
DS92LX2122SQ/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your DS92LX2122SQ/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for DS92LX2122SQ/NOPB?
For technical support, including DS92LX2122SQ/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your DS92LX2122SQ/NOPB requirements.
6.How does Aetrix verify that DS92LX2122SQ/NOPB is sourced from the original manufacturer or authorized distributors?
All DS92LX2122SQ/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that DS92LX2122SQ/NOPB meets industry standards.
7.What is the process for return or replacement of DS92LX2122SQ/NOPB?
All DS92LX2122SQ/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with DS92LX2122SQ/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The DS92LX2122SQ/NOPB part is unused and in its original packaging.
Return procedure for DS92LX2122SQ/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
DS92LX2122SQ/NOPB Tags

-
SN65HVS880PWPR
Texas Instruments

-
SN65HVS882PWPR
Texas Instruments

-
FIN3386MTDX
onsemi

-
FIN3385MTDX
onsemi

-
SN65LV1023ARHBR
Texas Instruments

-
SN65LV1023ADBR
Texas Instruments

-
SN65LV1224BDBR
Texas Instruments

-
SN65LVDS93ADGGR
Texas Instruments

-
SN65LVDS93DGGR
Texas Instruments

-
TDES954RGZT
Texas Instruments

-
SN65LV1224BRHBT
Texas Instruments

-
DS90UB914QSQE/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

