Texas Instruments DS99R104TSQX/NOPB

Overview

DS99R104TSQX/NOPB from Texas Instruments is a 24-bit LVDS deserializer that recovers embedded clock and data from a serial LVDS stream (3–40 MHz), outputs parallel LVCMOS data with RCLK, and asserts LOCK upon CDR lock. It features integrated 100 Ω input termination, 4 mA LVCMOS output drive, and supports AC-coupled STP interconnects up to 10 m. Used in flat-panel display timing controllers and industrial camera interfaces.

For engineers reviewing the DS99R104TSQX/NOPB datasheet, DS99R104TSQX/NOPB pinout, DS99R104TSQX/NOPB application, or DS99R104TSQX/NOPB equivalent, this page delivers verified technical context, exact pin functions per TI SNLS241D, real-world timing margins (RxIN_TOL_L/R = ±0.25 UI), and validated alternatives for display interface design.

Technical Context

The DS99R104TSQX/NOPB implements embedded-clock CDR without external reference, locking autonomously to incoming LVDS data using a PLL-based recovery circuit. It decodes DC-balanced 24:1 serialized streams and reconstructs parallel 24-bit data with precise skew control-balanced tROS/tROH across three output groups (ROUT[7:0], [15:8], [23:16]) and ±0.25 UI input jitter tolerance.

Its architecture includes on-chip filters for PLL stability, progressive turn-on (PTO) LVCMOS outputs to suppress SSO noise, and individual RPWDNB/REN controls for power-down sequencing. The receiver integrates 100 Ω differential input termination and supports user-selectable RCLK edge polarity via RRFB.

Key Specifications

Pinout & Package

DS99R104TSQX/NOPB is packaged in a 48-pin WQFN (6 mm × 6 mm, 0.4 mm pitch), thermally enhanced with exposed thermal pad. Pinout matches TI's PFB0048A (TQFP) and NJU0048D (WQFN) package footprints.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with DS99R104TSQX/NOPB, DS99R104TVS/NOPB offers identical functionality in TQFP but trades thermal efficiency for legacy compatibility, while SN65LVDS32 lacks CDR and parallel reconstruction-making it unsuitable as a drop-in replacement for embedded-clock deserialization tasks.

Availability

DS99R104TSQX/NOPB is available at Aetrix Electronics and suitable for flat-panel display interfaces, industrial camera links, automotive infotainment systems, and medical imaging modules requiring stable component supply and long-term lifecycle support.

Supply support for DS99R104TSQX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity solutions with over 50 years of innovation in high-reliability interface ICs.

The DS99R104TSQX/NOPB belongs to TI's LVDS SerDes chipset family, designed specifically for cost-sensitive, high-noise industrial and automotive display and imaging applications requiring robust embedded-clock recovery and minimal PCB routing complexity.

FAQ

What is the primary function of the DS99R104TSQX/NOPB in a SerDes link?

The DS99R104TSQX/NOPB is a 24-bit LVDS deserializer that recovers both clock and data from an embedded-clock serial stream generated by its companion DS99R103TSQX/NOPB. It outputs parallel LVCMOS data (ROUT[23:0]) and a recovered clock (RCLK), asserting the LOCK pin only when CDR lock is achieved and outputs are stable. This eliminates need for separate clock lines and simplifies high-speed interconnects.

Does the DS99R104TSQX/NOPB require an external reference clock to operate?

No, the DS99R104TSQX/NOPB does not require an external reference clock. Its embedded-clock CDR circuit autonomously locks to the incoming LVDS serial stream's embedded timing information. The LOCK pin goes high only after successful lock, confirming that RCLK and ROUT[23:0] are valid and synchronized-enabling true "plug-and-lock" operation without system-level clock coordination.

How does the DS99R104TSQX/NOPB handle timing skew across its 24-bit parallel outputs?

The DS99R104TSQX/NOPB mitigates timing skew by dividing ROUT[23:0] into three independent 8-bit groups (0–7, 8–15, 16–23), each with distinct setup/hold specifications relative to RCLK. Group-specific tROS/tROH values (e.g., (29/56)*tRCP for Group 1) ensure deterministic timing windows per group, allowing PCB layout to route each group with matched trace lengths-critical for pixel-data integrity in display applications.

What is the significance of the LOCK pin on the DS99R104TSQX/NOPB?

The LOCK pin on the DS99R104TSQX/NOPB is a synchronous status flag indicating successful CDR lock and data validity. It asserts high only when the PLL has acquired lock to the embedded clock and RCLK/ROUT outputs are stable and aligned. Unlike asynchronous indicators, LOCK is edge-aligned with valid data-making it ideal for enabling downstream logic (e.g., FPGA capture registers) without additional synchronization logic.

Can the DS99R104TSQX/NOPB be used with AC-coupled interconnects?

Yes, the DS99R104TSQX/NOPB supports AC-coupled interconnects via its integrated DC-balanced decode and on-chip 100 Ω differential termination on RIN+/RIN−. When paired with the DS99R103TSQX/NOPB's DC-balanced encoder, no external coding logic or biasing networks are needed-enabling direct coupling through 100 nF capacitors per differential pair, which simplifies cabling and improves noise immunity in long-reach applications.