Texas Instruments DS99R104TVSX/NOPB

Overview

DS99R104TVSX/NOPB from Texas Instruments is a 24-bit LVDS deserializer that recovers embedded clock and data from a serial LVDS stream (3–40 MHz), outputs parallel LVCMOS data with RCLK, and asserts LOCK upon CDR lock. It features integrated 100Ω receiver termination, 4 mA LVCMOS output drive, and supports AC-coupled STP interconnects in display and imaging systems.

For engineers reviewing the DS99R104TVSX/NOPB datasheet, DS99R104TVSX/NOPB pinout, DS99R104TVSX/NOPB application, or DS99R104TVSX/NOPB equivalent, this page delivers verified timing margins (±0.25 UI RxIN_TOL), power-down control (RPWDNB), DC-balanced decode, and real-world deserialization behavior - critical for high-reliability video link design and live-pluggable interfaces.

Technical Context

The DS99R104TVSX/NOPB implements a fully autonomous embedded-clock CDR architecture with no external reference required. Its PLL locks to the incoming LVDS data stream's transitions, recovering both bit clock and frame-aligned parallel data across 3–40 MHz input rates.

It decodes DC-balanced serial data using on-chip logic that ensures AC-coupling compatibility without external encoding. The deserializer organizes 24-bit outputs into three groups (ROUT[7:0], [15:8], [23:16]) with group-specific setup/hold timing relative to RCLK, and provides progressive turn-on (PTO) LVCMOS outputs to suppress SSO noise.

Key Specifications

Pinout & Package

DS99R104TVSX/NOPB is housed in a 48-pin WQFN package (7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are identical to the 48-pin TQFP variant (PFB0048A), enabling footprint interchangeability.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with DS99R104TVSX/NOPB, DS90CR288AMTDX/NOPB offers wider data bus and higher speed but adds external termination and removes hardware lock assurance; SN65LVDS32PW is a basic receiver only and cannot replace deserialization functionality.

Availability

DS99R104TVSX/NOPB is available at Aetrix Electronics and suitable for automotive digital clusters, industrial panel PCs, medical endoscopy systems, and avionics cabin displays requiring stable component supply and long-term lifecycle support.

Supply support for DS99R104TVSX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity solutions for industrial, automotive, and communications markets.

The DS99R104TVSX/NOPB belongs to TI's Serializer/Deserializer (SerDes) chipset family designed specifically for high-integrity, low-EMI video transport over cost-effective shielded twisted-pair cabling in space- and noise-constrained environments.

FAQ

What is the function of the LOCK pin on DS99R104TVSX/NOPB?

The LOCK pin on DS99R104TVSX/NOPB is an active-high output that asserts only after the internal CDR achieves stable lock to the incoming LVDS data stream and valid RCLK/ROUT data are present. It is synchronous to the recovered clock and serves as hardware-verified data integrity flag - essential for safe initialization in display and imaging systems. DS99R104TVSX/NOPB does not assert LOCK during transient lock acquisition or under loss-of-signal conditions.

Does DS99R104TVSX/NOPB require an external reference clock?

No, DS99R104TVSX/NOPB does not require an external reference clock. Its embedded-clock CDR circuit recovers both timing and data directly from the serial LVDS input stream (RIN+/RIN−). This enables true "plug-and-lock" operation without additional clock routing, making DS99R104TVSX/NOPB ideal for isolated or modular video links where clock distribution is impractical.

How does DS99R104TVSX/NOPB handle AC-coupled LVDS inputs?

DS99R104TVSX/NOPB supports AC-coupled LVDS inputs via internal DC-balanced decoding and integrated 100 Ω differential termination on RIN+/RIN−. No external biasing or encoding is required. The DC-balance algorithm ensures baseline wander correction across arbitrary data patterns, allowing reliable operation with 100 nF AC-coupling capacitors - a key enabler for long-cable or modular interconnects.

What is the purpose of RPWDNB on DS99R104TVSX/NOPB?

RPWDNB is the active-low receiver power-down control pin on DS99R104TVSX/NOPB. When pulled low, it places all ROUT[23:0] and RCLK outputs in TRI-STATE and shuts down the CDR PLL, reducing supply current to ≤50 µA. This enables dynamic power gating in multi-link systems or low-power standby modes without affecting the upstream serializer (DS99R103).

Can DS99R104TVSX/NOPB operate with non-repetitive or random data patterns?

Yes, DS99R104TVSX/NOPB uses RDL (Random Data Lock) technology to acquire CDR lock on arbitrary, non-repetitive data patterns - including live video streams. Unlike pattern-dependent deserializers, DS99R104TVSX/NOPB does not require training sequences or special sync words, enabling true live-pluggable operation in medical, automotive, and industrial video applications.