Texas Instruments DS99R105SQX/NOPB

Overview

DS99R105SQX/NOPB from Texas Instruments is a 24-bit LVDS serializer IC that converts parallel LVCMOS data (24-bit bus + clock) into a single DC-balanced serial LVDS stream with embedded clock, operating at 3–40 MHz (72–960 Mbps). It features user-selectable clock edge sampling (rising/falling), internal DC-balancing encoding, pre-emphasis control, and 48-pin WQFN packaging. It enables high-integrity video/data transmission over shielded twisted-pair cables in display interface applications.

For engineers reviewing the DS99R105SQX/NOPB datasheet, DS99R105SQX/NOPB pinout, DS99R105SQX/NOPB application, or DS99R105SQX/NOPB equivalent, key selection criteria include embedded-clock CDR compatibility, LVDS output voltage selectability (±400 mV / ±750 mV), AC-coupled interconnect support, and live-pluggable RDL lock behavior - all critical for noise-sensitive, cable-driven timing systems.

Technical Context

The DS99R105SQX/NOPB implements a fully transparent parallel-to-serial conversion using a PLL-based clock multiplication architecture synchronized to TCLK. Its DC-balanced 24:1 encoding eliminates baseline wander, enabling reliable AC-coupling without external coding logic. The integrated pre-emphasis circuit boosts high-frequency content to compensate for channel loss in long STP runs.

It supports progressive turn-on (PTO) LVCMOS outputs to suppress simultaneous switching output (SSO) noise, and includes on-chip PLL filters, internal 100 Ω LVDS termination, and individual power-down controls for transmitter (TPWDNB) and data enable (DEN). All LVCMOS inputs feature internal pulldowns for robust default-state behavior.

Key Specifications

Pinout & Package

DS99R105SQX/NOPB is housed in a 48-pin WQFN package (6 mm × 6 mm, 0.4 mm pitch) with exposed thermal pad. Pin assignments are optimized for signal integrity: dedicated analog/digital power domains (VDDDR/VSSDR, VDDT/VSST, VDDL/VSSL, VDDIT/VSSIT), split ground planes, and differential LVDS outputs (DOUT+, DOUT−) placed adjacent with controlled impedance routing paths.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS serializer applications.

Compared with DS99R105SQX/NOPB, DS99R107TVS/NOPB extends bandwidth but increases design complexity, while SN65LVDS31DR lacks essential serializer functions - making DS99R105SQX/NOPB the optimal balance of integration, cable drive, and ease of use for 3–40 MHz embedded display links.

Availability

DS99R105SQX/NOPB is available at Aetrix Electronics and suitable for display interface bridging, industrial camera links, automotive infotainment displays, and medical imaging backplanes requiring stable component supply and long-term manufacturability.

Supply support for DS99R105SQX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions.

The DS99R105SQX/NOPB belongs to TI's legacy LVDS SerDes chipset family, designed specifically for cost-sensitive, noise-resilient parallel-to-serial conversion in display, imaging, and industrial control systems - emphasizing plug-and-lock reliability and AC-coupled interoperability.

FAQ

What is the primary function of the DS99R105SQX/NOPB in a system?

The DS99R105SQX/NOPB is a 24-bit LVDS serializer that converts parallel LVCMOS data and clock into a single DC-balanced serial LVDS stream with embedded clock. Its core role is to replace wide parallel buses with a compact, noise-immune differential link - reducing PCB layer count, connector size, and EMI in display and imaging systems. DS99R105SQX/NOPB achieves this without external encoding logic or reference clocks.

Does the DS99R105SQX/NOPB require an external clock source for operation?

No, the DS99R105SQX/NOPB uses the incoming TCLK signal as its sole timing reference and generates the high-speed LVDS bit clock internally via PLL multiplication. It does not require an external oscillator or reference clock beyond TCLK. DS99R105SQX/NOPB locks to TCLK within 10 ms and maintains stable output even with ±33 ps RMS input jitter - eliminating complex clock distribution networks.

How does the DS99R105SQX/NOPB support AC-coupled interconnects?

The DS99R105SQX/NOPB incorporates on-chip DC-balancing encoding that ensures equal numbers of 1s and 0s over time, preventing baseline wander in AC-coupled paths. This eliminates the need for external Manchester or 8b10b encoders. DS99R105SQX/NOPB explicitly supports AC coupling via 100 nF capacitors on DOUT+/DOUT−, as confirmed in TI's SNLS242D datasheet Figure 11 and functional description.

What is the significance of the VODSEL pin on the DS99R105SQX/NOPB?

The VODSEL pin selects the LVDS output differential voltage: LOW configures ±400 mV (standard drive), HIGH configures ±750 mV (boosted drive). This allows DS99R105SQX/NOPB to adapt to channel loss - ±400 mV suffices for short PCB traces, while ±750 mV maintains signal integrity over longer shielded twisted-pair cables. DS99R105SQX/NOPB's datasheet specifies both values under "LVDS DC SPECIFICATIONS" with guaranteed min/max limits.

Can the DS99R105SQX/NOPB operate without the DS99R106 deserializer?

No - the DS99R105SQX/NOPB is designed exclusively as the transmitter half of a matched chipset with the DS99R106 deserializer. Its embedded-clock protocol, DC-balancing scheme, and RDL lock mechanism are co-optimized for that pairing. While it outputs valid LVDS, standalone use lacks clock recovery, parallel reconstruction, and LOCK status feedback - making DS99R105SQX/NOPB non-functional without DS99R106 or an equivalent CDR-capable receiver.