Texas Instruments DS99R105VS/NOPB

Overview

DS99R105VS/NOPB from Texas Instruments is a 24-bit LVDS serializer IC that converts parallel LVCMOS data (3–40 MHz clock) into a DC-balanced serial LVDS stream with embedded clock, enabling reliable transmission over shielded twisted-pair cable. It features user-selectable clock edge (rising/falling), internal DC balancing for AC-coupled interfaces, pre-emphasis control, and 48-pin WQFN packaging. Used in flat-panel display interconnects and industrial video links where skew reduction and EMI suppression are critical.

For engineers reviewing the DS99R105VS/NOPB datasheet, DS99R105VS/NOPB pinout, DS99R105VS/NOPB application, or DS99R105VS/NOPB equivalent, this page delivers verified functional identity, validated package mapping (48-pin WQFN), confirmed timing parameters (tDIS = 5 ns, tSD = 3.5T + 2.85 ns), real-world interface constraints (LVDS output differential voltage ±400 mV or ±750 mV), and two technically documented alternative serializers for 24-bit parallel-to-serial conversion.

Technical Context

The DS99R105VS/NOPB implements a PLL-based clock embedding architecture that accepts a 3–40 MHz parallel clock (TCLK) and encodes 24-bit parallel data into a single LVDS serial stream with no external reference required at the receiver. Its DC-balancing encoder ensures baseline wander immunity, supporting AC-coupled interconnects without external coding logic.

It integrates on-chip 100 Ω LVDS termination, programmable output drive strength (via VODSEL), pre-emphasis (PRE pin), and independent power-down controls (TPWDNB, DEN). The serializer's CDR-free design relies on precise timing alignment between TCLK and DIN[23:0], with balanced setup/hold (tDIS/tDIH = 5 ns each) and deterministic delay (tSD = 3.5 × clock period + 2.85 ns).

Key Specifications

Pinout & Package

DS99R105VS/NOPB is housed in a 48-pin WQFN package (7 mm × 7 mm, 0.5 mm pitch) with wettable flanks, optimized for thermal performance and automated optical inspection. Pin functions are validated per TI SNLS242D Rev D datasheet.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 24-bit parallel-to-LVDS serializer applications.

Compared with DS90C124 and SN65LVDS93, DS99R105VS/NOPB uniquely balances 24-bit integration, DC-balanced AC coupling, and 48-pin WQFN compactness for mid-range display interconnects - offering lowest BOM cost and simplest layout among functionally comparable serializers.

Availability

DS99R105VS/NOPB is available at Aetrix Electronics and suitable for flat-panel display interfaces, industrial camera links, automated test equipment, and avionics video distribution requiring stable component supply and long-term production continuity.

Supply support for DS99R105VS/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions.

The DS99R105VS/NOPB belongs to TI's LVDS Serializer/Deserializer chipset family, designed specifically for cost-effective, skew-immune video and imaging data transport in commercial and industrial display systems.

FAQ

What is the primary function of the DS99R105VS/NOPB in a video interface system?

The DS99R105VS/NOPB serves as a 24-bit parallel-to-LVDS serializer, converting RGB888 pixel data and a parallel clock into a single DC-balanced LVDS serial stream with embedded clock. In a video interface system, DS99R105VS/NOPB eliminates timing skew between data and clock lines, reduces EMI, and enables transmission over shielded twisted-pair cable - making it essential for flat-panel display interconnects and industrial camera links.

Does the DS99R105VS/NOPB require an external reference clock at the deserializer side?

No, the DS99R105VS/NOPB does not require an external reference clock at the deserializer side. Its architecture embeds clock information directly into the LVDS serial stream, allowing the companion DS99R106 deserializer to recover both clock and data using its internal CDR circuit. This eliminates clock distribution complexity and ensures DS99R105VS/NOPB systems operate with a single timing source at the transmitter.

How does the VODSEL pin affect signal integrity in the DS99R105VS/NOPB?

The VODSEL pin on the DS99R105VS/NOPB selects LVDS output differential voltage: LOW sets ±400 mV (suitable for short PCB traces), and HIGH sets ±750 mV (optimized for longer shielded twisted-pair cables up to 10 m). This adjustment directly impacts noise margin and eye opening - selecting VODSEL = H improves signal integrity under channel loss conditions without requiring external amplification or equalization.

Can the DS99R105VS/NOPB support AC-coupled interconnects without external encoding?

Yes, the DS99R105VS/NOPB supports AC-coupled interconnects without external encoding due to its integrated DC-balancing encoder/decoder. This feature ensures zero average DC offset in the LVDS stream, allowing use of simple 100 nF AC-coupling capacitors on DOUT+ and DOUT− lines - eliminating the need for complex 8b10b or Manchester encoding logic and reducing system component count.

What is the significance of the LOCK signal in systems using the DS99R105VS/NOPB and DS99R106?

The LOCK signal is generated by the DS99R106 deserializer and indicates successful PLL lock to the incoming serialized data stream from DS99R105VS/NOPB. When LOCK = HIGH, the deserializer has recovered a stable clock and validated data integrity - signaling the system controller that parallel output (ROUT[23:0] and RCLK) is valid and ready for use. This provides deterministic startup sequencing and fault detection in DS99R105VS/NOPB-based video links.