Texas Instruments DS99R106SQX/NOPB

Overview

DS99R106SQX/NOPB from Texas Instruments is a 24-bit LVDS deserializer IC that recovers embedded clock and converts serial LVDS data (3–40 MHz) into parallel LVCMOS outputs with ±4 mA drive strength, integrated 100 Ω receiver termination, and LOCK status flag - used in flat-panel display interconnects, industrial camera links, and automotive infotainment video backplanes.

For engineers reviewing the DS99R106SQX/NOPB datasheet, DS99R106SQX/NOPB pinout, DS99R106SQX/NOPB application, or DS99R106SQX/NOPB equivalent, key selection criteria include its 3–40 MHz clock range, RCLK/RIN± timing tolerance (±0.25 UI), DC-balanced decode for AC-coupled cabling, and support for live-pluggable operation via RDL coding and PTO LVCMOS outputs.

Technical Context

The DS99R106SQX/NOPB implements a fully autonomous embedded-clock CDR architecture with no external reference required; it locks to incoming serial data using internal PLLs with on-chip filters and validates integrity via RDL (Random Data Lock) coding. Its deserialization path includes input latch, DC-balance decode, clock recovery, output latch, and progressive turn-on (PTO) LVCMOS drivers.

It supports three parallel output groups (ROUT[7:0], [15:8], [23:16]) with group-specific setup/hold timing relative to RCLK, balanced TSETUP/THOLD margins, and individual power-down control via RPWDNB. The receiver accepts differential LVDS inputs (RIN+/RIN−) with integrated 100 Ω termination and tolerates ±0.25 UI input jitter margin at 3–40 MHz.

Key Specifications

Pinout & Package

DS99R106SQX/NOPB is housed in a 48-pin WQFN package (7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are validated per TI SNLS242D Rev. D (April 2013) and match the DS99R106 pin diagram (Figure 19).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LVDS deserializer applications.

Compared with DS99R106SQX/NOPB, the DS99R106TVS/NOPB offers identical functionality in a larger, thermally less efficient package, while SN65LVDS32 lacks CDR, parallel output, and LOCK signaling - making it unsuitable for embedded-clock deserialization tasks.

Availability

DS99R106SQX/NOPB is available at Aetrix Electronics and suitable for flat-panel display interfaces, industrial machine vision links, and automotive infotainment backplanes requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for DS99R106SQX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions.

The DS99R106SQX/NOPB belongs to TI's LVDS SerDes chipset family, designed specifically for cost-effective, low-skew, AC-coupled video and imaging data transport over shielded twisted-pair cables in industrial and automotive environments.

FAQ

What is the primary function of the DS99R106SQX/NOPB in a SerDes link?

The DS99R106SQX/NOPB is the deserializer component of the DS99R105/DS99R106 chipset. It receives a 24-bit LVDS serial stream with embedded clock, recovers timing via its CDR circuit, and outputs synchronized 24-bit LVCMOS parallel data and RCLK. Its LOCK pin confirms stable lock acquisition - a core function distinguishing DS99R106SQX/NOPB from basic LVDS receivers.

Does the DS99R106SQX/NOPB require an external reference clock to operate?

No. The DS99R106SQX/NOPB uses embedded-clock recovery and does not require an external reference clock. Its CDR circuit extracts timing directly from the incoming LVDS data stream, enabling autonomous lock acquisition - a defining feature confirmed in the Functional Description section of the DS99R106SQX/NOPB datasheet (SNLS242D).

How does the DS99R106SQX/NOPB handle input jitter and data pattern variability?

The DS99R106SQX/NOPB tolerates ±0.25 UI of input jitter (RxIN_TOL_L/R) across 3–40 MHz and achieves lock on arbitrary random data via RDL coding - eliminating need for training sequences. This behavior is verified in DS99R106SQX/NOPB's Deserializer Switching Characteristics table and Initialization section, ensuring robust operation in live-plug scenarios.

What is the significance of the three ROUT output groups in the DS99R106SQX/NOPB?

The DS99R106SQX/NOPB splits its 24-bit parallel outputs into three groups (ROUT[7:0], [15:8], [23:16]) with group-specific setup/hold timing relative to RCLK. This design reduces inter-group skew and allows optimized PCB routing - a feature explicitly defined in DS99R106SQX/NOPB's Deserializer Switching Characteristics and pin descriptions.

Can the DS99R106SQX/NOPB be used without the companion DS99R105 serializer?

No - the DS99R106SQX/NOPB is designed exclusively for use with the DS99R105 serializer. Its CDR, DC-balance decode, and RDL locking mechanism are optimized for the specific encoding and timing protocol of the DS99R105. TI documentation states the devices form a matched chipset; interoperability with third-party serializers is not supported or characterized for DS99R106SQX/NOPB.