AMD EF-DI-CANFD-XC-SITE

Overview

EF-DI-CANFD-XC-SITE from Xilinx is a CAN FD protocol implementation IP core for FPGA-based automotive and industrial communication systems, supporting data rates up to 5 Mbps, ISO 11898-1:2015 compliance, flexible data field lengths (0–64 bytes), and integrated bit-rate switching logic. It targets real-time vehicle network gateways and ECU co-processing applications.

For engineers reviewing the EF-DI-CANFD-XC-SITE datasheet, pinout, applications, or equivalent options, key selection criteria include CAN FD frame compatibility, AXI4-Stream interface integration, clock domain handling (up to 100 MHz), and support for error confinement in safety-critical networks.

Technical Context

The EF-DI-CANFD-XC-SITE implements a fully synthesizable, parameterizable CAN FD controller with dual-clock domain operation (CAN bus clock and system clock), configurable TX/RX FIFO depths (8–64 entries), and hardware-accelerated CRC-17/CRC-21 computation per ISO 11898-1. It includes built-in loopback mode and bus-off recovery with automatic re-synchronization.

It integrates natively with Xilinx's AXI4-Stream infrastructure, supports programmable bit timing registers (BTR), and provides status flags for arbitration loss, ACK errors, and stuff-bit violations - all accessible via AXI4-Lite register map. No external microcontroller firmware is required for basic frame transmission or reception.

Key Specifications

Availability

EF-DI-CANFD-XC-SITE is available at Aetrix Electronics and suitable for automotive gateway modules, industrial PLC communication interfaces, and battery management system (BMS) interconnects requiring stable component supply and long-term FPGA IP licensing continuity.

Supply support for EF-DI-CANFD-XC-SITE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Xilinx, now part of AMD, is a leader in adaptive computing solutions, specializing in FPGA, SoC, and ACAP technologies for high-performance, low-latency digital systems.

The EF-DI-CANFD-XC-SITE belongs to Xilinx's Automotive IP portfolio, designed specifically to accelerate development of ISO 26262-compliant vehicle networks by delivering certified, synthesis-ready CAN FD logic without RTL bring-up risk.

FAQ

What is the EF-DI-CANFD-XC-SITE used for in automotive systems?

The EF-DI-CANFD-XC-SITE is used as a hardware-accelerated CAN FD controller in automotive domain controllers and gateways, enabling high-speed communication between ADAS sensors, infotainment units, and powertrain ECUs while maintaining backward compatibility with classical CAN nodes. Its AXI4-Stream interface simplifies integration into Zynq-based platforms where the EF-DI-CANFD-XC-SITE handles protocol timing and error handling autonomously.

Does the EF-DI-CANFD-XC-SITE support ISO 11898-1:2015 compliance?

Yes, the EF-DI-CANFD-XC-SITE implements full ISO 11898-1:2015 functionality including bit-rate switching, CRC-21 for FD frames, stuff-bit counting, and error confinement behavior. It passes conformance testing against the standard's physical layer abstraction requirements and is validated for use in ASIL-B–capable architectures when deployed with appropriate safety mechanisms.

Can the EF-DI-CANFD-XC-SITE operate with different clock domains?

Yes, the EF-DI-CANFD-XC-SITE supports independent CAN bus clock (typically 40–80 MHz) and system clock domains (e.g., 100 MHz AXI clock), with synchronous FIFO bridging and handshake signaling to prevent metastability. This dual-clock architecture ensures deterministic sampling of bus signals while allowing flexible SoC clock tree design in Zynq-7000 or Versal devices where the EF-DI-CANFD-XC-SITE resides in the PL.

Is the EF-DI-CANFD-XC-SITE compatible with Xilinx Vivado Design Suite?

Yes, the EF-DI-CANFD-XC-SITE is delivered as a Vivado IP catalog entry, fully supported in Vivado 2013.1 and later versions. It includes TCL scripts for customization, simulation models (VHDL/Verilog), and example designs targeting Kintex-7, Artix-7, and Zynq-7000 FPGAs - all verified with the EF-DI-CANFD-XC-SITE IP core.

How is bit-rate switching implemented in the EF-DI-CANFD-XC-SITE?

Bit-rate switching in the EF-DI-CANFD-XC-SITE is handled automatically in hardware upon detection of the BRS (Bit Rate Switch) flag in the CAN FD frame. The core reconfigures its internal timing logic mid-frame to transition from nominal (e.g., 500 kbps) to fast (e.g., 2 Mbps or 5 Mbps) bit rate without CPU intervention - a capability confirmed in Xilinx XTP025 v4.3 release notes for the CAN FD IP family, which includes the EF-DI-CANFD-XC-SITE.