AMD EFR-DI-25GBASE-KR-PROJ

Overview

EF-R-DI-25GBASE-KR-PROJ from Xilinx is a licensable IP core implementing the 25GBASE-KR Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) for FPGA-based 25 Gb/s Ethernet interfaces. It supports IEEE 802.3by Clause 74 FEC, Clause 73 Auto-Negotiation, and Clause 72.6.10 Link Training, operates at 25.78125 Gb/s line rate, and integrates with Xilinx GTY transceivers on UltraScale+ devices for data center switch uplinks and server NICs.

For engineers reviewing the EFR-DI-25GBASE-KR-PROJ datasheet, pinout, applications, or equivalent options, this page delivers verified technical context, latency metrics, transceiver interface mapping, RS-FEC capability, and licensing-aware selection guidance for 25G KR PHY integration in Zynq UltraScale+ MPSoC and Kintex/Virtex UltraScale+ platforms.

Technical Context

The EFR-DI-25GBASE-KR-PROJ implements a standards-compliant 25GBASE-KR PCS/PMA stack targeting Xilinx UltraScale+ FPGAs. It embeds Clause 74 shortened cyclic FEC (2112,2080), Clause 73 Auto-Negotiation state machines, and Clause 72.6.10 Link Training logic - all synchronized to the GTY transceiver's serial lane interface.

It operates exclusively in PCS-only mode with 25GMII user interface, requires external MAC, and delivers measured latency of 71.03 ns at 390.625 MHz core clock. The design uses asynchronous gearbox between GTY and logic domains and supports runtime configuration via AXI4-Lite status/control interface.

Key Specifications

Availability

EFR-DI-25GBASE-KR-PROJ is available at Aetrix Electronics and suitable for data center switch uplinks, high-performance server NICs, and FPGA-accelerated network appliances requiring stable component supply, long-term IP license continuity, and certified 25G KR PHY integration support.

Supply support for EFR-DI-25GBASE-KR-PROJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Xilinx (now part of AMD) is a semiconductor company specializing in adaptive computing solutions, including FPGA, SoC, and ACAP platforms for high-performance networking, AI acceleration, and embedded systems.

EFR-DI-25GBASE-KR-PROJ belongs to Xilinx's LogiCORE IP portfolio for high-speed Ethernet, designed specifically to enable standards-compliant 25G KR physical layer implementation in UltraScale+ FPGAs without requiring custom RTL development.

FAQ

What is the primary function of the EFR-DI-25GBASE-KR-PROJ IP core?

The EFR-DI-25GBASE-KR-PROJ IP core implements the 25GBASE-KR Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) for Xilinx UltraScale+ FPGAs. It provides full Clause 74 FEC, Clause 73 Auto-Negotiation, and Clause 72.6.10 Link Training functionality - but does not include a MAC. EFR-DI-25GBASE-KR-PROJ must be paired with an external MAC (e.g., EF-DI-25GEMAC-PROJ) to form a complete 25G Ethernet subsystem.

Which Xilinx device families support EFR-DI-25GBASE-KR-PROJ?

EFR-DI-25GBASE-KR-PROJ is validated for Zynq UltraScale+ MPSoC, Virtex UltraScale+, Kintex UltraScale+, Virtex UltraScale, and Kintex UltraScale FPGAs. It relies on the GTY transceiver architecture and requires specific package-compatible GTY quads with adequate reference clock routing. Device support is confirmed in Vivado IP Catalog and PG210 v2.4 documentation.

Does EFR-DI-25GBASE-KR-PROJ include RS-FEC (Clause 108)?

No. EFR-DI-25GBASE-KR-PROJ implements only Clause 74 FEC (shortened cyclic code). RS-FEC per IEEE 802.3by Clause 108 is provided by a separate license key (ieee802d3_25g_rs_fec_full) and is not part of the EFR-DI-25GBASE-KR-PROJ feature set. That capability is available in distinct configurations such as EF-DI-25GEMAC-PROJ when combined with appropriate licensing.

What user interface does EFR-DI-25GBASE-KR-PROJ provide?

EFR-DI-25GBASE-KR-PROJ uses a 25GMII interface: a 66-bit parallel bus (64 data bits + 2 control bits) operating at 390.625 MHz. It does not support XGMII or AXI4-Stream. The 25GMII interface connects directly to an external MAC, and status/control is accessible via optional AXI4-Lite register interface.

Is EFR-DI-25GBASE-KR-PROJ a standalone purchasable product or a software license?

EFR-DI-25GBASE-KR-PROJ is a fee-based, licensable IP core delivered as encrypted RTL within the Vivado Design Suite. It is not a physical component but a digital intellectual property module requiring a valid license key (xxv_eth_basekr) for synthesis, implementation, and bitstream generation. Licensing is managed through Xilinx/AMD and enforced at Vivado Synthesis and Implementation checkpoints.