AMD EFR-DI-25GBASE-KR-RLL

Overview

EF-DI-25GBASE-KR-RLL from Xilinx is a licensable IP core implementing the 25GBASE-KR Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) with optional Clause 74 Forward Error Correction (FEC), Auto-Negotiation (AN), and Link Training (LT), targeting UltraScale+ and UltraScale FPGAs for high-speed data center interconnects. It operates at 25.78125 Gb/s line rate, supports 64-bit AXI4-Stream user interface, delivers 71.03 ns latency in PCS-only mode, and integrates with Xilinx GTY transceivers.

For engineers reviewing the EFR-DI-25GBASE-KR-RLL datasheet, pinout, applications, or equivalent options, this page provides verified technical context, latency benchmarks, transceiver I/O mapping, RS-FEC integration details, and FPGA-specific clocking requirements essential for 25G Ethernet subsystem integration in Top-of-Rack switches and server NICs.

Technical Context

The EFR-DI-25GBASE-KR-RLL implements IEEE 802.3by Clause 49 64B/66B encoding/decoding and Clause 74 shortened cyclic (2112,2080) FEC at 25.78125 Gb/s, with full support for Auto-Negotiation and Link Training per IEEE 802.3. It interfaces directly with Xilinx GTY transceivers via differential SerDes lanes and provides synchronous AXI4-Stream handshaking at 390.625 MHz.

This PCS/PMA-only variant excludes MAC logic and requires external MAC or processor interface via 64-bit AXI4-Stream; it does not include IEEE 1588 timestamping or TSN preemption features - those are restricted to MAC+PCS variants per Table 1-1 of PG210 v2.4.

Key Specifications

Pinout & Package

EFR-DI-25GBASE-KR-RLL is a synthesizable RTL IP core, not a physical component. It has no package or pinout. Its interface consists of configurable digital ports mapped to FPGA logic and I/O resources. Implementation requires assignment to GTY transceiver sites and clock routing to dedicated high-speed clock networks.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 25G PCS/PMA applications.

Compared with EF-DI-25GBASE-KR-PROJ, EFR-DI-25GBASE-KR-RLL delivers guaranteed 71.03 ns latency and optimized timing closure for KR backplane use cases, whereas the PROJ variant prioritizes flexibility over deterministic low latency. The MAC+PCS bundle adds significant logic overhead and latency, making it unsuitable for pure PHY acceleration roles.

Availability

EFR-DI-25GBASE-KR-RLL is available at Aetrix Electronics and suitable for Top-of-Rack switches, server NICs, and AI accelerator interconnects requiring stable component supply, long-term FPGA IP licensing continuity, and certified 25GBASE-KR compliance.

Supply support for EFR-DI-25GBASE-KR-RLL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Xilinx, now part of AMD, is a leader in adaptive computing, delivering FPGA, SoC, and ACAP technologies for high-performance, low-latency system design.

EFR-DI-25GBASE-KR-RLL belongs to the 10G/25G High Speed Ethernet Subsystem IP family, designed specifically for FPGA-based 25G Ethernet PHY offload in data center switching, server acceleration, and high-bandwidth compute interconnects.

FAQ

What is the exact latency of EFR-DI-25GBASE-KR-RLL in 25G PCS-only mode?

The measured latency of EFR-DI-25GBASE-KR-RLL is 71.03 ns in 25G PCS-only configuration, as documented in Table 2-1 of PG210 v2.4. This value represents end-to-end delay through the PCS logic only, excluding GTY transceiver latency, and is achieved under low-latency buffer bypass mode. EFR-DI-25GBASE-KR-RLL guarantees this latency bound for timing-critical 25G backplane applications.

Does EFR-DI-25GBASE-KR-RLL include MAC functionality?

No, EFR-DI-25GBASE-KR-RLL is a PCS/PMA-only IP core and does not include MAC logic. It provides only the physical coding sublayer (64B/66B encode/decode, scrambling/descrambling) and PMA interface to GTY transceivers. MAC functionality must be implemented separately - for example, using EF-DI-25GEMAC-PROJ - or provided by an external processor or soft-core.

Which Xilinx device families support EFR-DI-25GBASE-KR-RLL?

EFR-DI-25GBASE-KR-RLL is supported on Zynq UltraScale+ MPSoC, Virtex UltraScale+, Kintex UltraScale+, Virtex UltraScale, and Kintex UltraScale FPGAs. Support is confirmed in the "Supported Device Family" row of the IP Facts table in PG210 v2.4. It requires GTY transceivers and is not compatible with older GTH or GTX-based devices.

Is Clause 108 RS-FEC included in EFR-DI-25GBASE-KR-RLL?

No, EFR-DI-25GBASE-KR-RLL implements only Clause 74 shortened cyclic FEC (2112,2080). Clause 108 RS-FEC is excluded per PG210 v2.4 feature matrix and Table 1-1, which lists RS-FEC support only for "25G MAC with PCS" and "Runtime switchable 10G/25G MAC+PCS" variants - not for PCS-only configurations like EFR-DI-25GBASE-KR-RLL.

What clock frequencies are required to operate EFR-DI-25GBASE-KR-RLL at 25G?

EFR-DI-25GBASE-KR-RLL requires a 390.625 MHz AXI4-Stream clock (tx_clk_out/rx_clk_out) for 64-bit interface operation and a differential 156.25 MHz reference clock (refclk_p0/n0) for GTY transceiver startup. These frequencies are fixed by the 25.78125 Gb/s line rate and 64B/66B encoding ratio, and deviations will violate IEEE 802.3by compliance.