AMD EFR-DI-25GBASE-KR-SITE

Overview

EF-DI-25GBASE-KR-SITE from Xilinx is a licensable IP core implementing the 25GBASE-KR Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA), compliant with IEEE 802.3 Clause 74 and Clause 108 RS-FEC, operating at 25.78125 Gb/s serial line rate, supporting Auto-Negotiation and Link Training for backplane applications in UltraScale+ FPGAs.

For engineers reviewing the EFR-DI-25GBASE-KR-SITE datasheet, pinout, applications, or equivalent options, this IP delivers production-ready, synthesizable RTL for 25G KR backplane Ethernet PHY integration - with verified latency (71.03 ns), AXI4-Stream interface, GTY transceiver coupling, and RS-FEC/shortened cyclic FEC options.

Technical Context

This IP implements the full BASE-KR PCS/PMA stack - including 64B/66B encoding/decoding, scrambling/descrambling, RS-FEC (Clause 108), shortened cyclic FEC (Clause 74), Auto-Negotiation state machine (Clause 73), and Link Training (Clause 72.6.10) - targeting Xilinx UltraScale+ GTY transceivers. It operates exclusively in 25G mode (25.78125 Gb/s) and does not support runtime 10G/25G switching.

The core interfaces via differential SerDes lanes (rx_serdes_data_p0/n0, tx_serdes_data_p0/n0) and provides a 64-bit AXI4-Stream user interface clocked at 390.625 MHz. It requires asynchronous resets (gt_tx_reset, gt_rx_reset, ctl_gt_reset_all) and dual-phase reference clocks (refclk_p0/n0) aligned to GTY transceiver timing requirements.

Key Specifications

Availability

EFR-DI-25GBASE-KR-SITE is available at Aetrix Electronics and suitable for high-speed backplane interconnects, 25G server NICs, and TOR switch PHY layers requiring stable component supply, long-term IP license continuity, and FPGA-based Ethernet PHY customization.

Supply support for EFR-DI-25GBASE-KR-SITE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Xilinx (now part of AMD) is a semiconductor company specializing in adaptive computing platforms, including FPGAs, SoCs, and programmable logic IP cores for high-performance networking, AI acceleration, and embedded systems.

EFR-DI-25GBASE-KR-SITE belongs to Xilinx's LogiCORE IP portfolio for high-speed Ethernet, designed specifically to enable standards-compliant 25G backplane connectivity in UltraScale+ FPGA-based infrastructure equipment.

FAQ

What is the primary function of the EFR-DI-25GBASE-KR-SITE IP core?

The EFR-DI-25GBASE-KR-SITE IP core implements the full 25GBASE-KR Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA), including Clause 74 FEC, Clause 108 RS-FEC, Auto-Negotiation, and Link Training - enabling standards-compliant 25G backplane Ethernet PHY functionality in Xilinx UltraScale+ FPGAs. It does not include MAC logic and must be paired with a separate MAC IP such as EFR-DI-25GEMAC-SITE.

Does EFR-DI-25GBASE-KR-SITE support both 10G and 25G operation?

No. EFR-DI-25GBASE-KR-SITE is strictly a 25G-only implementation operating at 25.78125 Gb/s. It does not support 10GBASE-KR (10.3125 Gb/s) or runtime 10G/25G switching. For dual-rate capability, the distinct EFR-DI-25GEMAC-PROJ or EFR-DI-25GEMAC-SITE + EFR-DI-25GBASE-KR-SITE combination is required - but EFR-DI-25GBASE-KR-SITE itself is 25G-only.

Which Xilinx device families are supported by EFR-DI-25GBASE-KR-SITE?

EFR-DI-25GBASE-KR-SITE targets only Xilinx UltraScale+ architecture devices: Zynq UltraScale+ MPSoC, Virtex UltraScale+, and Kintex UltraScale+. It requires GTY transceivers and is incompatible with 7-series, UltraScale (non-Plus), or Versal devices. Device support is verified per Vivado IP Catalog and PG210 v2.4 documentation.

What interface does EFR-DI-25GBASE-KR-SITE use to connect to user logic?

EFR-DI-25GBASE-KR-SITE uses a 64-bit AXI4-Stream interface clocked at 390.625 MHz (tx_clk_out/rx_clk_out) for packet data transfer, plus dedicated asynchronous control signals (gt_tx_reset, gt_rx_reset, ctl_gt_reset_all) and differential SerDes I/O (rx_serdes_data_p0/n0, tx_serdes_data_p0/n0). It does not provide XGMII or 25GMII interfaces - those are reserved for MAC+PCS variants.

Is a license required to use EFR-DI-25GBASE-KR-SITE in hardware?

Yes. EFR-DI-25GBASE-KR-SITE is a fee-based licensed IP core. The license key xxv_eth_basekr is mandatory for synthesis, implementation, and bitstream generation in Vivado. Without a valid license, Vivado halts generation during synthesis or implementation with a licensing error - no functional bitstream can be produced.