AMD EFR-DI-25GBASE-KR-WW

Overview

EF-DI-25GBASE-KR-WW from Xilinx is a licensable IP core implementing the 25GBASE-KR Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA), compliant with IEEE 802.3 Clause 74 and Clause 108 RS-FEC, operating at 25.78125 Gb/s line rate with support for Auto-Negotiation (AN) and Link Training (LT). It integrates with Xilinx GTY transceivers and delivers <71 ns latency in PCS-only mode for 25G applications in data center switch uplinks and server NICs.

For engineers reviewing the EFR-DI-25GBASE-KR-WW datasheet, pinout, applications, or equivalent options, this page provides verified technical context, latency benchmarks, transceiver interface mapping, RS-FEC implementation details, and validated alternative configurations for 25G KR-based designs.

Technical Context

The EFR-DI-25GBASE-KR-WW implements a standards-compliant 25GBASE-KR PCS/PMA stack including Clause 74 Forward Error Correction (FEC) with shortened cyclic code (2112, 2080) and optional Clause 108 Reed-Solomon FEC. It operates exclusively in PCS-only mode with 25GMII user interface and requires external MAC integration.

It targets Xilinx UltraScale+ and UltraScale FPGAs, interfaces directly with GTY transceivers via differential SerDes lanes (rx_serdes_data_p0/n0, tx_serdes_data_p0/n0), and uses asynchronous reset domains (gt_tx_reset, gt_rx_reset) synchronized internally. Clocking relies on 25.78125 GHz reference clock inputs (refclk_p0/n0) and generates tx_clk_out/rx_clk_out outputs aligned to AXI4-Stream timing.

Key Specifications

Availability

EFR-DI-25GBASE-KR-WW is available at Aetrix Electronics and suitable for data center top-of-rack switches, high-performance server NICs, and FPGA-based network accelerators requiring stable component supply, long-term IP license continuity, and certified 25G KR PHY implementation.

Supply support for EFR-DI-25GBASE-KR-WW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Xilinx (now AMD Adaptive SoC Business Unit) is a semiconductor company specializing in programmable logic devices, FPGA-based system-on-chip solutions, and high-speed connectivity IP for data center, networking, and aerospace applications.

The EFR-DI-25GBASE-KR-WW belongs to Xilinx's 10G/25G High Speed Ethernet Subsystem product line, engineered specifically for FPGA-based 25G KR physical layer implementation in backplane and copper cable interconnects requiring AN/LT and multi-level FEC.

FAQ

What is the primary function of the EFR-DI-25GBASE-KR-WW IP core?

The EFR-DI-25GBASE-KR-WW is a licensable Xilinx IP core that implements the 25GBASE-KR Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA), including Clause 74 and Clause 108 RS-FEC, Auto-Negotiation, and Link Training. It does not include a MAC; it connects to external MAC logic via 25GMII and interfaces directly with GTY transceivers. The EFR-DI-25GBASE-KR-WW enables standards-compliant 25G KR PHY functionality in UltraScale+ FPGAs.

Does EFR-DI-25GBASE-KR-WW support both 10G and 25G operation?

No - EFR-DI-25GBASE-KR-WW is strictly a 25G-only configuration. It operates at 25.78125 Gb/s and implements 25GBASE-KR features including Clause 108 RS-FEC. For dual-rate 10G/25G KR support, Xilinx offers separate part numbers such as EF-DI-25GBASE-KR-PROJ/SITE, but EFR-DI-25GBASE-KR-WW is designated exclusively for 25G KR operation per its ordering documentation and PG210 v2.4 specification.

Which FPGA families are supported by EFR-DI-25GBASE-KR-WW?

EFR-DI-25GBASE-KR-WW is validated for Xilinx Virtex UltraScale+, Kintex UltraScale+, and Zynq UltraScale+ MPSoC families. It requires GTY transceivers and is not compatible with older GTH or GTYE4 transceivers. Device support is constrained to those UltraScale+ parts with GTY banks meeting the 25.78125 Gb/s serial line rate and required reference clock stability.

What user interface does EFR-DI-25GBASE-KR-WW provide?

EFR-DI-25GBASE-KR-WW provides a 25GMII interface: a 64-bit parallel bus running at 390.625 MHz, delivering 25 Gb/s aggregate bandwidth. This interface connects to external MAC logic or testbenches and is distinct from XGMII (used for 10G). No AXI4-Stream or AXI4-Lite control interface is included in the base EFR-DI-25GBASE-KR-WW configuration per PG210 Table 1-2 and port descriptions.

Is a license required to use EFR-DI-25GBASE-KR-WW in hardware?

Yes - EFR-DI-25GBASE-KR-WW requires a fee-based license key (xxv_eth_basekr and ieee802d3_25g_rs_fec_full) for synthesis, implementation, and bitstream generation in Vivado. The license is enforced at Vivado Synthesis and Implementation checkpoints. Without valid licensing, generation halts with error; simulation-only use may be permitted under evaluation terms, but hardware deployment requires purchased entitlement.