AMD EFR-DI-25GEMAC-PROJ

Overview

EF-R-DI-25GEMAC-PROJ from Xilinx is a synthesizable 10G/25G Ethernet Media Access Controller (MAC) + Physical Coding Sublayer (PCS) IP subsystem targeting Zynq UltraScale+ MPSoC, Virtex UltraScale+, and Kintex UltraScale+ FPGAs. It implements IEEE 802.3 Clause 49 BASE-R at 10.3125 Gb/s or 25.78125 Gb/s, delivers 46.08 ns latency at 25G with 64-bit AXI4-Stream interface, and supports runtime switchable 10G/25G operation in a single configuration.

For engineers reviewing the EFR-DI-25GEMAC-PROJ datasheet, pinout, applications, or equivalent options, this IP core enables high-bandwidth, low-latency Ethernet datapath integration in FPGA-based network accelerators, smart NICs, and data center interconnect subsystems - with verified support for RS-FEC (Clause 108), IEEE 1588 timestamping, and 802.1cm frame preemption.

Technical Context

The EFR-DI-25GEMAC-PROJ integrates a full 64-bit MAC and Clause 49 PCS, interfacing directly with Xilinx GTY transceivers via 25.78125 Gb/s serial lanes. Its datapath uses 64B/66B encoding/decoding, includes configurable preamble and inter-frame gap, and supports asynchronous gearbox mode for SerDes clock domain crossing.

It provides dual-clock-domain AXI4-Stream I/O (rx_clk_out and tx_clk_out), optional AXI4-Lite control/status register map, and hardware-accelerated pause processing per IEEE 802.3 Annex 31D. Latency is fixed at 46.08 ns for 25G operation at 390.625 MHz core clock, with no FIFO buffering in low-latency mode.

Key Specifications

Availability

EFR-DI-25GEMAC-PROJ is available at Aetrix Electronics and suitable for FPGA-based network accelerators, smart NICs, data center top-of-rack switches, and time-sensitive industrial controllers requiring stable component supply and long-term IP licensing continuity.

Supply support for EFR-DI-25GEMAC-PROJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Xilinx (now part of AMD) is a fabless semiconductor company specializing in adaptive computing platforms, including FPGA, SoC, and ACAP technologies for high-performance digital logic implementation.

The EFR-DI-25GEMAC-PROJ belongs to Xilinx's LogiCORE IP portfolio and was designed specifically for high-throughput, low-latency Ethernet subsystem integration in UltraScale+ architecture FPGAs used in cloud infrastructure and real-time networking applications.

FAQ

What is the exact function of EFR-DI-25GEMAC-PROJ in an FPGA design?

EF-R-DI-25GEMAC-PROJ is a parameterized, synthesizable IP core that implements a complete 25G Ethernet Media Access Controller and Physical Coding Sublayer (MAC+PCS) for Xilinx UltraScale+ FPGAs. It handles frame assembly/disassembly, 64B/66B encoding/decoding, CRC generation/checking, pause frame processing, and direct interface to GTY transceivers - all within programmable logic, without requiring external PHY chips.

Does EFR-DI-25GEMAC-PROJ include built-in transceivers or require external GTY usage?

EF-R-DI-25GEMAC-PROJ does not contain physical transceivers. It is a logic-only IP subsystem that must be instantiated alongside Xilinx GTY transceivers on supported devices (e.g., Virtex UltraScale+, Kintex UltraScale+, Zynq UltraScale+ MPSoC). The core connects to GTY via defined serial I/O ports (tx_serdes_data_p0/n0, rx_serdes_data_p0/n0) and relies on device-native SerDes resources.

What license requirements apply to EFR-DI-25GEMAC-PROJ?

EF-R-DI-25GEMAC-PROJ requires the xxv_eth_mac_pcs license key for full functionality in Vivado Design Suite. This is a fee-based license distinct from the free BASE-R PCS/PMA core. The license enables synthesis, implementation, and bitstream generation - and must be installed before core generation or flow execution.

Can EFR-DI-25GEMAC-PROJ operate at both 10G and 25G speeds in the same bitstream?

Yes - EFR-DI-25GEMAC-PROJ supports runtime switchable 10G/25G operation. The core can be configured during initialization to run at either 10.3125 Gb/s or 25.78125 Gb/s using the same RTL netlist and bitstream, with dynamic reconfiguration of clocking, datapath width, and PCS parameters controlled via AXI4-Lite registers.

Is IEEE 1588 timestamping supported in EFR-DI-25GEMAC-PROJ, and at which layer?

Yes - EFR-DI-25GEMAC-PROJ supports IEEE 1588 v2 1-step and 2-step timestamping at the MAC layer. Timestamps are inserted into PTP event messages (Sync, Delay_Req) with sub-nanosecond alignment to the physical transmit/receive edges, enabling precise time synchronization in TSN and industrial automation applications.